Cesar0182
Member level 5
Greetings ... a couple of days ago I'm trying to translate a project verilog to vhdl with Vivado 2017.3, and in some lines of code is used by the SLL operator, and for it is the first time that I use it. These lines generate the following error that is shown in the attached image.
The original lines in verilog are the following.
Can someone help me with this problem please? Thanks in advance.
The original lines in verilog are the following.
Code:
parameter Hotlink_SDMA_Base = 0;
parameter [31:0] used_engine_mask = 8'hff << Hotlink_SDMA_Base | 1'b0; // Set 8 bits = 4 Hotlink ports * 2 engines
parameter [25:0] used_wbus_chan_mask = 8'hff << Hotlink_SDMA_Base | 1'b0; // Set 8 bits = 4 Hotlink ports * 2 wbus_chans
Can someone help me with this problem please? Thanks in advance.