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Error: Default expression of interface objects is not globally static

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Cesar0182

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Greetings ... a couple of days ago I'm trying to translate a project verilog to vhdl with Vivado 2017.3, and in some lines of code is used by the SLL operator, and for it is the first time that I use it. These lines generate the following error that is shown in the attached image.
The original lines in verilog are the following.

Code: 
parameter Hotlink_SDMA_Base = 0;
parameter [31:0] used_engine_mask = 8'hff << Hotlink_SDMA_Base  | 1'b0;  // Set 8 bits = 4 Hotlink ports * 2 engines
parameter [25:0] used_wbus_chan_mask = 8'hff << Hotlink_SDMA_Base  | 1'b0; // Set 8 bits = 4 Hotlink ports * 2 wbus_chans

Can someone help me with this problem please? Thanks in advance.
generic_error.PNG
 

I just corrected this, but I still have the same problem.
generic_error2.PNG
 

I don't believe that SSL is allowed on an integer type it can only be used on a one dimensional array with elements of bit or boolean type.

In this case use the first code but change the type to std_logic_vector(15 downto 0) for the two SSL lines.
 

Integers cannot be shifted nor can they be acted on logically, because they have no binary representation directly.
 

thanks for the help ... to tell you that I have managed to correct the error, implementing the following lines.


Hotlink_SDMA_Base : integer := 0;
used_engine_mask : std_logic_vector(31 downto 0) := (X"FF" SLL Hotlink_SDMA_Base) OR '0';
used_wbus_chan_mask : std_logic_vector(25 downto 0) := (X"FF" SLL Hotlink_SDMA_Base) OR '0'

Although when using these parameters in an "if", I have the syntax error that is shown in the attached image, I have verified that the problem is not the parameter but the declaration of the "if".
Could someone please tell me what mistake I am making in this statement that I can not see?

synth_error.PNG
 

We need the failing source code lines. The error message in post #6 has nothing to do with the source code you have shown so far.
 

I apologize, I was wrong about the image
sintax_error.PNG
 
Last edited:

Cesar0182 said:
thanks for the help ... to tell you that I have managed to correct the error, implementing the following lines.


Hotlink_SDMA_Base : integer := 0;
used_engine_mask : std_logic_vector(31 downto 0) := (X"FF" SLL Hotlink_SDMA_Base) OR '0';
used_wbus_chan_mask : std_logic_vector(25 downto 0) := (X"FF" SLL Hotlink_SDMA_Base) OR '0'

[/ATTACH]
Click to expand...

This code has errors as the constants you have created do not match the sizes of arrays specified. The literals are only 8 bits, whereas the arrays are 32 bits and 26 bits. The literals (or results of the initializing function)must match the length.
 

Code: 
if ([B][COLOR="#FF0000"]NOT[/COLOR][/B] something(i) = '1') then
You can't perform NOT in a compare operation. Compare against '0' and remove the NOT

Code: 
if (something(i) = '0') then

You need to read a tutorial or a book on VHDL before writing code.
 

ads-ee said:
You can't perform NOT in a compare operation. Compare against '0' and remove the NOT
Click to expand...

Of course you can. The syntax error is because the if statement is inside a generate, rather than in procedural code. This error appears twice.
 

I think like TrickyDicky, there is some way to solve this, since this is based on the following verilog lines.

Code: 
generate
   genvar   jdx;
   for (jdx=0; jdx<=31; jdx = jdx+1)
     begin : used_engine_mask_blk

        if( ~used_engine_mask[jdx] )
          begin
             assign o_cpi_sdma_enc             [jdx] =  1'b0;
             assign o_cpi_sdma_record_added_tk [jdx] =  1'b0;
             assign o_cpi_sdma_ff_almost_full  [jdx] =  1'b0;
             assign sdma_dq_vector             [jdx] = 32'h0;
             assign o_cpi_sdma_eof             [jdx] =  1'b0;
             assign sdma_record_size_vector    [jdx] =  9'h0;
          end
     end
endgenerate

// Tie off unused wbus channels
generate
   genvar   vdx;
   for (vdx=0; vdx<=25; vdx = vdx+1)
     begin : wbus_chan_mask_blk

        if( ~used_wbus_chan_mask[vdx] )
          begin
             assign o_cpi_wbus_enable [vdx] =  1'b0;
             assign wbus_fws_vector   [vdx] =  5'h1F; // Point unused wbus fifo's to uppermost memory window
             assign o_cpi_wbus_clk    [vdx] =  i_clk;
             assign o_cpi_wbus_ren    [vdx] =  1'b1;  // Any data written to FIFO's will drain
          end
     end
endgenerate
 

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