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Emitter-coupled logic operation

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promach

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For the operation of emitter-coupled logic and sedra smith book,

1) Compared to CMOS, why ECL is the fastest logic family given that it requires so many gates to propagate to output Y (T5 emitter node) ?

2) Why current drawn from the power supply remains constant during switching and regardless of which state the ECL is in ?

3) How is the reference voltage Vr made insensitive to temperature and PSRR according to calculation made below ?

350px-ECL_structure_1000.jpg



bWkQTrO.png
 

I don't know all the details about the inner workings of ECL, but the main thing is that the transistors operate in the linear region. In other words, they don't go into saturation as other logic families do. This is why ECL is faster,;you don't have to pay the penalty of waiting for a transistor to come out of saturation.
 
2) Why current drawn from the power supply remains constant during switching and regardless of which state the ECL is in ?

The current in the long tailed pair (T3 and T4) is constant.
So irrespective of the states , this current is shared by T3 and T4.
It either decrease or increase only in individual transistor(say T3or T4 ) but total remains the same.
 

I don't know all the details about the inner workings of ECL, but the main thing is that the transistors operate in the linear region. In other words, they don't go into saturation as other logic families do. This is why ECL is faster,;you don't have to pay the penalty of waiting for a transistor to come out of saturation.
That's true for bipolar logic such as TTL, but CMOS does not saturate and has no saturation delay.
And modern CMOS logic is quite fast, running at many GHz in present microprocessors.
 

ECL is not faster than CMOS anymore. It was. It could
be if anyone cared to bring out a new bipolar (SiGe)
logic family, but integration is where it's at if you want
raw speed and many gates. And of course III-V like
InP has been kicking ECL's butt for decades. TRW was
running hundreds of GHz main clock back in the '80s,
ECL could maybe hang at 1/100 of that (self toggle
frequency is one thing, useful circuits with combo
stages between the 'flops is quite another).

Various sub-families have different reference schemes.
Some tried for constant delay over temp (good for
boards and boards of logic that may be quite temps
at the part level). That means a reference that fights
the slowdown by making a non-constant tail current
profile. The scheme shown in the pic has diodes that
take less of the (Vbe-VEE) headroom when hot, so
more net voltage and (depending on resistor tempco)
likely more base voltage and a higher VR -> higher Itail.

You can find good info in the older Motorola ECL
databooks (10K, 100K, ECLiPS, ...) but it's a fading
interest generally.
 

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