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rtl code to find the smallest

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stanford

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lets say we have 4 inputs

input [7:0] in[4];

To find the smallest number we want to use 4 comparators for the fastest implementation.
i.e compare (in[0], in[1]), (in[1], in[2]), (in[2], in[3]), (in[0], in[3]). From this result, you will get 4 outputs.

c0 = in[0] > in[1];
c1 = in[1] > in[2];
c2 = in[2] > in[3];
c3 = in[0] > in[3];

then we need a decoder to find the smallest. How does this decoder look like?

thanks
 
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I don't see four inputs, do you mean input [7:0] in[1:4];

Are you looking for combinational or registered (clocked) logic? In both cases, why don't you write down a behavioral or structural description?
 

I don't see four inputs, do you mean input [7:0] in[1:4];

Are you looking for combinational or registered (clocked) logic? In both cases, why don't you write down a behavioral or structural description?

sorry, edited the original post with more details
 

This will not work. As an example, you don't compare in[0] and in[2], so if they both are smaller than in[1] and in[3], you don't know which of them is the smallest.
I think you need 6 comparators to do this in one clock cycle.
What is the output? Is it the smallest number, or is it an index to tell which number is the smallest?

Do you really need to do this in one clock cycle? A pipeline with 3 comparators will have the same throughput, but will add one clock cycle latency.

Edit:
How many bits in the input values? Maybe a 3-comparator structure is the best solution, even if a pipeline isn't used.
 
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I don't see four inputs, do you mean input [7:0] in[1:4];

Code Verilog - [expand]
1
2
3
input [7:0] in[4]
// which is equivalent to
input [7:0] in[0:3]


does give you 4 input bytes, it's syntax they added in SV, module port arrays now work unlike in Verilog.

I prefer using packed arrays for ports as they can then be used with VHDL arrays, at least in the various test cases I've built to check that. I'm not sure you can use Verilog unpacked arrays with the array definition of VHDL I'm not sure the component/modules will bind properly.

Code:
assign c0 =                   (in[0] < in[1]) & (in[0] < in[2]) & (in[0] < in[3]);
assign c1 = (in[1] < in[0]) &                   (in[1] < in[2]) & (in[1] < in[3]);
assign c2 = (in[2] < in[0]) & (in[2] < in[1]) &                   (in[2] < in[3]);
assign c3 = (in[3] < in[0]) & (in[3] < in[1]) & (in[3] < in[2]);
You need something like this to check for the lowest value. In this code only one of the c# will be asserted as only one of the values is less than all the others. If there are two or more values that are the smallest and identical then none of the assignments will be active. If you need that behavior you can change the < to <=. In that case you'll potentially see all of them active if all inputs are the same value.
 

This will not work. As an example, you don't compare in[0] and in[2], so if they both are smaller than in[1] and in[3], you don't know which of them is the smallest.
I think you need 6 comparators to do this in one clock cycle.
What is the output? Is it the smallest number, or is it an index to tell which number is the smallest?

Do you really need to do this in one clock cycle? A pipeline with 3 comparators will have the same throughput, but will add one clock cycle latency.

Edit:
How many bits in the input values? Maybe a 3-comparator structure is the best solution, even if a pipeline isn't used.

How would you do it with 3 comparators? could you please explain?
 

I am a VHDL person, and the combinatorial version with 3 comparators would look something like this:
Code:
smallest_of_0_1 <= input_0 when input_0 < input_1 else input_1;
smallest_of_2_3 <= input_2 when input_2 < input_3 else input_3;
smallest <= smallest_of_0_1 when smallest_of_0_1 < smallest_of_2_3 else smallest_of_2_3;

This can be pipelined to achieve the needed throughput.
 

I am a VHDL person, and the combinatorial version with 3 comparators would look something like this:
Code:
smallest_of_0_1 <= input_0 when input_0 < input_1 else input_1;
smallest_of_2_3 <= input_2 when input_2 < input_3 else input_3;
smallest <= smallest_of_0_1 when smallest_of_0_1 < smallest_of_2_3 else smallest_of_2_3;

This can be pipelined to achieve the needed throughput.

yes but this is not the fastest since the comparison is one after another. I wanted to do all the comparison in parallel and decode.
 

Did you look at post #5? I gave you the method to do this in parallel and the result is a one-hot decode of which input port has the smallest value.

You realize that your lack of detail requirements in the original posted question leaves a lot of room for interpretation...
 

yes but this is not the fastest since the comparison is one after another. I wanted to do all the comparison in parallel and decode.

define 'fastest'. you gotta pick throughput or latency, can't have the cake and eat it too.
 
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