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[SOLVED] Help to translate verilog code lines to vhdl

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Cesar0182

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I tell you that I am new to this forum, I have limited knowledge of vhdl, but I am a novice in verilog. A couple of days ago I'm trying to translate a module from a verilog project to vhdl, but this makes use of other modules, I have managed to translate this, but I have problems translating the following lines of a module
Code: 
`define WBUSRANGE 32*idx+31:32*idx  // Incrementing indexes within generate below
generate
   genvar   idx;
   for (idx=0; idx<=25; idx = idx+1)

      assign o_wbus_count[10*idx+9:10*idx] = wbus_count[idx];

      wire wen = i_wbus_enable[idx] & i_wbus_wen & upper_adrs_match &
             & (i_wbus_addr[20:16] == i_wbus_fws[5*idx+4:5*idx]);

      wire almost_full_d = i_wbus_enable[idx] & ( ff_write_count > 
      Almost_Full_Depth );

      dreg_clr #(1) dc_amf( .c( i_aur_clk ), .ar( i_rst ), .e( 1'b1 ), .d( 
      almost_full_d ), .q( almost_full[idx] ) );

      assign o_wbus_waddr[`WBUSRANGE] = {13'h0, ff_dout[50:32]};
      assign o_wbus_wdata[`WBUSRANGE] = ff_dout[31:0];

   end
endgenerate

Can someone please help me with this, thanks in advance.
 

I don't understand why you would have a problem with this code, it's very straight forward...

Use a VHDL generate and a for loop.
As you can see translating the code should be relatively easy...
Code Verilog - [expand]
1

assign o_wbus_count[10*idx+9:10*idx] = wbus_count[idx];

Code VHDL - [expand]
1

o_wbus_count(10*idx+9 downto 10*idx) <= wbus_count(idx);


Translating between the two usually requires knowing both languages. The bigger question is why would you bother translating a perfectly good piece of Verilog code into VHDL. Simulators and synthesis tools are almost all mixed mode simulators/synthesizers by default.
 

Thanks for responding ads-ee ... the reason is that I need to pass this project verilog to vhdl, I know which lines are relative easy to translate, but there is a special line that I can not find the way to obtain its equivalent in vhdl, since that is the definition of a range of bits, how can I define this variable range in vhdl.

`define WBUSRANGE 32*idx+31:32*idx // Incrementing indexes within generate below
 

Thanks to your help I have successfully translated my previous code.

Code: 
genvar : for idx in 0 to 25 generate

	  o_wbus_count [10*idx+9 downto 10*idx] <= wbus_count(idx); 

      wire wen 	<= i_wbus_enable(idx) and i_wbus_wen and upper_adrs_match and ( '1' when i_wbus_addr(20 downto 16) = i_wbus_fws(5*idx + 4 downto 5*idx) esle '0'); 

      wire casi_full_d = i_wbus_enable(idx) & ('1' when ff_write_count> Almost_Full_Depth else '0');

      dc_amf : dreg_clr generic map (1)  
      port map(
      	c 	=> i_aur_clk, 
      	ar  => i_rst,
      	e 	=> '1', 
      	d 	=> almost_full_d,
      	q 	=> almost_full(idx)
      );

      o_wbus_waddr (32*idx+31 downto 32*idx)  <= "0000000000000" & ff_dout (50 downto 32);
      o_wbus_wdata (32*idx+31 downto 32*idx)  <= ff_dout (31 downto 0);
end generate genvar;

but I mention that in this project there are cases with the following format:

Code: 
generate
   genvar   idx;
   for (idx=0; idx<=25; idx = idx+1)
     begin : sdma_engines
     //sequential statements
   end
endgenerate

I tried to keep it as it is in verilog, but it does not work ... what would be the equivalent in vhdl for
Code: 
begin : sdma_engines ?
 
Last edited by a moderator:

a define is just like a C define the stuff aster the identifier WBUSRANGE is substituted wherever the define is used. So just copy paste 32*idx... wherever the define is used. You also have to substitute the : with downto in the VHDL, e.g. like I did in my previous post.

- - - Updated - - -

Looking at the code this could be done in VHDL with an array instead of all the bit-vector slicing. This Verilog code was probably written before (or by someone not familiar with) Systemverilog introduced the use of packed arrays.

- - - Updated - - -

begin : sdma_engines is a label, this ends up as the indexed portion of the hierarchical name in the netlist.

I don't recall the specific generate syntax of VHDL, but it's pretty easy to do a google search for it.
 

Error: Indexed name is not to std_ulogic_vector

Greetings ... I tell you that I am doing a project in Vivado 2017.3 and I am having the error shown in the attached image and I do not understand why.
std_ulogic_vector_error.PNG
Here I leave the lines of code that I am using.
Code: 
entity g1_wbus_client_fifos is
           port(
                 ...
                 ...
                 o_wbus_count   : OUT std_logic_vector(259 DOWNTO 0);    
           );
end g1_wbus_client_fifos;

architecture Behavioral of g1_wbus_client_fifos is

          SIGNAL wbus_count       : std_logic_vector(9 DOWNTO 0);

          begin

          genvar : for idx in 0 to 25 generate
    
                begin       
               
                o_wbus_count(10*idx+9 downto 10*idx)    <= wbus_count(idx);
                ...
                ...  
          end generate genvar;
end Behavioral;

Someone who can help me with this error please.
 
Last edited by a moderator:

The definition of wbus_count doesn't make sense, it must be two-dimensional to make the assignment work.

Presently RHS is std_logic and LHS 10 bit std_logic_vector, thus the error message.

I wonder how wbus_count is defined in the related Verilog code, expect an array of vector.
 

I apologize for this last post, I thought I had created a new topic ... as I had previously commented I am translating a project from verilog to vhdl, and as you indicate the problem is in the wbus_count statement. The original verilog statement for wbus_count is as follows.

wire [9:0] wbus_count [0:25];

How do I declare this expression in VHDL?
 

Yes you created a new topic, but according forum rules it's not appropriate, they say
avoid creating multiple threads with similar questions, ask all related questions in one thread.
Click to expand...

That's clearly a related question, without the original Verilog code, nobody can understand what you are trying to achieve.

You'll write something like

Code VHDL - [expand]
1
2

type  wbus_count_type is array(0 to 25) of std_logic_vector(9 downto 0);
signal wbus_count : wbus_count_type;
 

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