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[SOLVED] Problem related to monte carlo simulation

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skj999

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i am designing a self-calibrated dynamic comparator. for that purpose i used to calculate the offset of comparator after calibration. For calculating the offset, i used a verilog code for 2:1 MUX. By doing this i get satisfactory results.

Now i have to do monte carlo simulation of self-calibrated dynamic comparator. But due to use of verilog code of multiplexer, monte carlo simulation is not running.
error 5052 is displayed "no statistical data is generated for the test"


is there any way of doing monte carlo simulation including verilog code and schematic both ?????
 

Also, calibration always has a residue and the residue
is what you live with in production. Residue can depend
on attributes not tested at WAT, like the skew between
the overlap capacitances and thresholds of NMOS, PMOS
devices in all of the switches (affecting charge injection
balance, which can only be designed to center, not span).
Span is what you're after with Monte Carlo analysis.

Look to how simulator paths and such may change between
regular and MC modes - maybe you are losing some veriloga
include-path, or losing the compile activity that loads the
C-code version?

What's wrong with substituting a switch from analogLib?
 
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    skj999

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cadence virtuoso(spectre)
 

i have included the mos model file(mc) only in simulation.

actually i want accurate results for offset. For this high speed clk (ns) is required for comparator. So i used a mux (verilog code). But the calibration process required clk in microseconds.
 

i need the histogram plot of offset of calibrated comoparator. monte carlo simulation also verify the efficiency of calibration technique for different mismatches.
 

For calculating the offset, i used a verilog code for 2:1 MUX.
So i used a mux (verilog code).
Use correct terminology.
If you refer "verilog" without showing simulator you use, it means Verilog-HDL or Verilog-D.

cadence virtuoso(spectre)
You use Cadence Spectre, so you use Verilog-A.
You do mixed level simulation of Transistor and Behavioral levels.

But due to use of verilog code of multiplexer,
monte carlo simulation is not running.
error 5052 is displayed "no statistical data is generated for the test"
is there any way of doing monte carlo simulation including verilog code
and schematic both ?????
There is no problem in monte-calro simulation even if you use mixed level netlist.

Simply there is no statistical description in your model files.
Surely confirm your model files.
https://www.edaboard.com/showthread.php?382100#2
 

Also, calibration always has a residue and the residue
is what you live with in production. Residue can depend
on attributes not tested at WAT, like the skew between
the overlap capacitances and thresholds of NMOS, PMOS
devices in all of the switches (affecting charge injection
balance, which can only be designed to center, not span).
Span is what you're after with Monte Carlo analysis.

Look to how simulator paths and such may change between
regular and MC modes - maybe you are losing some veriloga
include-path, or losing the compile activity that loads the
C-code version?

What's wrong with substituting a switch from analogLib?

I am sorry but is what is WAT?
 

PCM (process control monitor) devices are what WAT
(wafer acceptance test) criticizes.
 

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