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Using gate oxide capacitance for Op-Amp Compensation

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Junus2012

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Dear friends,

I designed two stage Op-Amp, I compensated my design using Poly capacitor, I needed a value of 4 PF for getting my phase margin, then I replaced the poly capacitor with mosfet transistor connected as a capacitor, now I am getting the same phase margin and or GBW as it was with poly, However I saved like 80 % area,

My question is that when MOS transistor is providing me with same capacitance value with less area, why I don't see by literature people doing it this way, is there some sideeffect which I dont know with this method ?

Note: my second stage is push pull amplifier so i need two capacitors one at the top with the PMOS and other down with the NMOS output transistor.


Thank you in advance
Best Regards
 

Issues include linearity / distortion and poorer high
frequency behaviors due to the "access resistance".
Highly doped poly plates will have lower ESR than
a MOS cap. MOS caps need to have the right bias
for their construction and generally you'd prefer a
depletion-mode FET for capacitor duty so that the
C-V swing happens outside signal * common mode
ranges. MOS caps also have the bottom plate to
substrate (N cap in P) or well (P cap in Nwell) that
is a stray signal / loss / leakage consideration,
while a POP cap is truly DC isolated and linear
beyond the rails.
 
Thank you freebird for your nice explanation,,

I agree with you with the point of linearity/distortion point, this is why the author suggested to use PMOS and NMOS transistors to cancel the non-linearity of each other, the source you kindly can see from

https://ieeexplore.ieee.org/document/272096
 

Compensation capacitor is connected to high-swing node and MOS capacitance has a strong dependence on Vgs (see C-V curve), which means for higher amplitudes the effective capacitance will drop dramatically. It can cause ringing on certain output voltage levels.
A trade-off can be between stability and area to use MOM or MIM capacitor above the MOS to improve linearity, other method is to use native device, or better is the MOS varactor (not equal with depletion mode FET), or the mentioned NMOS/PMOS together (IEEE is not available for unregistered users, I cannot verify it to you).
 

It's a pay-wall for me, but I can suggest you look carefully
at what happens by superposition of two "bent" capacitors -
do you really cancel, or do you end up "bent half as much,
but now at both ends" - then having a common mode problem
at both ends of the output swing, leaving you "no place to
hide"?
 

I am sure you are right, however I still cannot imagine what is the exact structure of this two bent capacitors, is it in the IEEE article?? In my understanding an NMOS and a PMOS with common gate, which is connected to the output, and the source-drains are connected to PMOS/NMOS cascode's source in the 1st stage. This can cause capacitance fall at both ends of the output swing, which is also a trade-off, it limits headroom.
By the way I am curious what is your opinion of this arrangement, do you think is it a waste of area or it can help a bit?
 
Last edited:

Dear Friends,

with the simulation with the MOSFET capacitor I am getting clean pulse response with good linearity and stability,,, I am saving 80% of the area comparing to normal capacitor
 

Simulate stability at the middle and at the edge of the output common-mode levels, compare them. Phase/gain margin can drop a lot at the edges. If step response is good in typical it doesn't mean the circuit will work in reality.
 
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