sarmadmahmood969
Newbie level 1
I have a VHDL code in which I call different modules. Here I god error that unknown formal identifier. I don't know how to tackle this error. I am new in VHDL, I put so much of my time but not succeeded. Here is the code:
This is the error:
If you please help me to resolve the error. I will be very thankful to you.
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 --****************************************************************************** -- * -- Copyright (C) 2014 Altera Corporation * -- * -- ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS & STRATIX * -- are Reg. U.S. Pat. & Tm. Off. and Altera marks in and outside the U.S. * -- * -- All information provided herein is provided on an "as is" basis, * -- without warranty of any kind. * -- * -- Module Name: mult8x8 File Name: mult8x8.vhd * -- * -- Module Function: This file contains the top level module for the * -- 8x8 multiplier * -- * -- REVISION HISTORY: * --****************************************************************************** -- Insert library and use clauses LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; -- Begin entity declaration for top-level "mult8x8" ENTITY mult8x8 IS -- Begin port declartion PORT ( -- Declare control inputs "clk", "start" and "reset_a" clk, start, reset_a : IN STD_LOGIC; -- Declare data inputs "dataa" and "datab" dataa, datab : IN UNSIGNED(7 DOWNTO 0); -- Declare multiplier output "product8x8_out" product8x8_out : OUT UNSIGNED(15 DOWNTO 0); -- Declare seven segment display outputs seg_a, seg_b, seg_c, seg_d, seg_e, seg_f, seg_g, done_flag : OUT STD_LOGIC ); -- End entity END ENTITY mult8x8; -- Begin architecture ARCHITECTURE logic OF mult8x8 IS -- Declare all lower level components COMPONENT adder PORT ( dataa, datab : IN UNSIGNED (15 DOWNTO 0); sum : OUT UNSIGNED (15 DOWNTO 0) ); END COMPONENT adder; ---################################################## -- complete component instantiations -- the components were created in the prior labs --- ############### ---- --- YOUR LOGIC HERE ---- COMPONENT mult4x4 PORT( dataa, datab : IN UNSIGNED(3 DOWNTO 0); product : OUT UNSIGNED(7 DOWNTO 0) ); END COMPONENT mult4x4; COMPONENT mux4 PORT( mux_in_a, mux_in_b: IN UNSIGNED(3 DOWNTO 0); mux_sel : IN STD_LOGIC; mux_out : OUT UNSIGNED(3 DOWNTO 0) ); END COMPONENT mux4; COMPONENT shifter Port ( input: IN UNSIGNED (7 DOWNTO 0); shift_cntrl : IN UNSIGNED (1 DOWNTO 0); shift_out : OUT UNSIGNED (15 DOWNTO 0) ); END COMPONENT shifter; COMPONENT counter PORT ( clk, aclr_n : IN STD_LOGIC; count_out : OUT UNSIGNED (1 DOWNTO 0) ); END COMPONENT counter; COMPONENT mult_control PORT ( clk, reset_a, start : IN STD_LOGIC; count : IN UNSIGNED (1 DOWNTO 0); input_sel, shift_sel : OUT UNSIGNED(1 DOWNTO 0); state_out : OUT UNSIGNED(2 DOWNTO 0); done, clk_ena, sclr_n : OUT STD_LOGIC ); END COMPONENT mult_control; COMPONENT seven_segment_cntrl Port ( input : in UNSIGNED (2 downto 0); seg_a : out STD_LOGIC; seg_b : out STD_LOGIC; seg_c : out STD_LOGIC; seg_d : out STD_LOGIC; seg_e : out STD_LOGIC; seg_f : out STD_LOGIC; seg_g : out STD_LOGIC); END COMPONENT seven_segment_cntrl; COMPONENT reg16 Port( clk, clk_ena, sclr_n : IN STD_LOGIC; datain: IN UNSIGNED (15 DOWNTO 0); reg_out : OUT UNSIGNED (15 DOWNTO 0) ); END COMPONENT reg16; --- ############### ---- -- Declare internal signals to use as wires to connect blocks -- used these signals to connect up all the components -- you should not need anymore signals --- SIGNAL aout, bout : UNSIGNED(3 DOWNTO 0); SIGNAL product : UNSIGNED(7 DOWNTO 0); SIGNAL shift_out, sum, product8x8 : UNSIGNED(15 DOWNTO 0); SIGNAL count, shift : UNSIGNED(1 DOWNTO 0); SIGNAL state_out : UNSIGNED(2 DOWNTO 0); SIGNAL clk_ena, sclr_n, start_n : std_logic; SIGNAL sel : UNSIGNED(1 DOWNTO 0); BEGIN -- Start SIGNAL requires inversion before connecting to counter start_n <= not(start); -- Connect blocks per schematic in the lab manual -- this port map is completed u1: mux4 PORT MAP (mux_in_a => dataa(3 DOWNTO 0), mux_in_b => dataa(7 DOWNTO 4), mux_sel => sel(0), mux_out => aout(3 DOWNTO 0)); u2: mux4 PORT MAP (mux_in_a => dataa(3 DOWNTO 0), mux_in_b => dataa(7 DOWNTO 4), mux_sel => sel(0), mux_out => aout(3 DOWNTO 0)); u3: mult4x4 PORT MAP (aout => dataa (3 DOWNTO 0), bout => datab (3 DOWNTO 0), product => product(7 DOWNTO 0)); u4: shifter PORT MAP (product => input (7 DOWNTO 0), shift => shift_cntrl (1 DOWNTO 0), shift_out => shift_out (15 DOWNTO 0)); u5: counter PORT MAP (clk => clk, start => aclr_n, count => count_out (1 DOWNTO 0)); u6: mult_control PORT MAP (clk => clk, reset_a => reset_a, start => start, count => count (1 DOWNTO 0), sel => input_sel (1 DOWNTO 0), shift => shift_sel (1 DOWNTO 0), state_out => state_out (2 DOWNTO 0), done => done, clk_ena => clk_ena, sclr_n => sclr_n); u7: reg16 PORT MAP (clk => clk, clk_era => clk_ena, sclr_n => sclr_n, sum => datain (15 DOWNTO 0), product8x8 => reg_out (15 DOWNTO 0)); u8: adder PORT MAP (shift_out => dataa (15 DOWNTO 0), product8x8 => datab (15 DOWNTO 0), sum => sum (15 DOWNTO 0)); u9: seven_segment_cntrl PORT MAP (state_out => input (2 downto 0), seg_a => seg_a, seg_b => seg_b, seg_c => seg_c, seg_d => seg_d, seg_e => seg_e, seg_f => seg_f, seg_g => seg_g); product8x8_out <= product8x8; -- End architecture END ARCHITECTURE logic;
This is the error:
Code:
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(151): (vcom-1484) Unknown formal identifier "aout".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(152): (vcom-1484) Unknown formal identifier "bout".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(155): (vcom-1136) Unknown identifier "input".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(156): (vcom-1136) Unknown identifier "shift_cntrl".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(155): (vcom-1484) Unknown formal identifier "product".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(156): (vcom-1484) Unknown formal identifier "shift".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(160): (vcom-1136) Unknown identifier "aclr_n".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(161): (vcom-1136) Unknown identifier "count_out".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(160): (vcom-1484) Unknown formal identifier "start".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(161): (vcom-1484) Unknown formal identifier "count".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(167): (vcom-1136) Unknown identifier "input_sel".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(168): (vcom-1136) Unknown identifier "shift_sel".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(170): (vcom-1136) Unknown identifier "done".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(167): (vcom-1484) Unknown formal identifier "sel".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(168): (vcom-1484) Unknown formal identifier "shift".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(177): (vcom-1136) Unknown identifier "datain".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(178): (vcom-1136) Unknown identifier "reg_out".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(175): (vcom-1484) Unknown formal identifier "clk_era".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(177): (vcom-1484) Unknown formal identifier "sum".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(178): (vcom-1484) Unknown formal identifier "product8x8".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(181): (vcom-1484) Unknown formal identifier "shift_out".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(182): (vcom-1484) Unknown formal identifier "product8x8".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(187): (vcom-1136) Unknown identifier "input".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(187): (vcom-1484) Unknown formal identifier "state_out".
** Error: E:/Fiverr/VHDL/VHDLCounterMultiplier/ModelSimdo/mult8x8.vhd(201): VHDL Compiler exiting
If you please help me to resolve the error. I will be very thankful to you.
Last edited by a moderator: