Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Design of a linear low-dropout voltage regulator in 0.18um cmos technology

Status
Not open for further replies.

chenkhai95

Newbie level 4
Joined
Feb 12, 2019
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
36
This is my schematic circuit using cadence software. Can anyone teach how to simulate the circuit in transient and ac simulation. Thanks.
Capture.PNG

Table below shows the dimension and parameter for the ldo.
table1.PNG
table2.PNG

Figure below shows the dc simulation result but I not sure whether is correct or not.
graph1.PNG
graph2.PNG
graph3.PNG

Please help me and if there is any resources kindly share me thanks.
 

Why are your input diff pair transistors so different in size?
 

Your pass FET is tiny and you have not said what the
range of load current might be. Nor what the range of
supply and output voltage setpoint may be. It appears
the stack height is over-large, as you don't enter
regulation until 1.5V and you are using all 1.8V
transistors. Despite everything being cascoded you
seem to show a not-great PSRR (w/ curvature) in the
first sim plot. Your feedback ladder appears to be
taking a few hundred uA, which might be too much
for the small pass FET (?) at modest overdrive and
linear-region. You "test" it by imposing much less
external load current - kooky.
 
Why are your input diff pair transistors so different in size?

Because I need to make all transistor to operate in saturation region. But at last i still cant make it by changing its width and length. So, what i can do to solve this problem. Thanks.
 

Thanks for the reply.
Here is my parameter for the design.
Input voltage = 1.65 V to 2 V
Output voltage = 1.6 V
Load current range = 9uA to 1.1mA
Is it possible to make that?
 

Because I need to make all transistor to operate in saturation region. But at last i still cant make it by changing its width and length. So, what i can do to solve this problem. Thanks.

Get rid of some stack height, which eats headroom.

Not all transistors get to be in saturation, all the time.
Regardless what you may think you want or "need".
Sometimes you just have to deal with that.

- - - Updated - - -

Thanks for the reply.
Here is my parameter for the design.
Input voltage = 1.65 V to 2 V
Output voltage = 1.6 V
Load current range = 9uA to 1.1mA
Is it possible to make that?

Possible? Probably.

You need to first get to a pass FET which will throw
2mA @ VTP-1V (or so) and 50mV Vds at slow*cold
(worst case VT) and slow*hot (worst case IDsat@Vgs)
and leak less than 1uA @ fast*hot, Vds=0.5V (make that
Vds=2V, if this LDO is supposed to also remove power
(e.g. for standby current spec).

Your pass FET should for sure come from the ESD library
(if FETs are there) or have ESD rules checked in the
symbol & PCell (when you get to layout). That's a pin-pin
pinata device application.
 

May i know how to perform the transient analysis and ac analysis for the circuit. How to setup and need to place what component in the schematic in order to perform the analysis. For example, I need to find out line regulation, load regulation, transient response, open-loop gain and phase.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top