[ADS] Filter simulation with spiral inductor

[pragash]

im simulating a filter in ADS with two spiral inductors (coil) at the layer 3 and layer 4.

however, my layer 1 has RF traces and components, layer 2 is GND, layer 3 is a coil and layer 4 is another coil. i selected GND layer as slot. the rest of the layers are strip layers with finite copper thickness (not sheet metal). However, im not getting correlation between layout simulation and circuit simulation with "TL-multilayer".

i have a feeling that ADS not simulating inner layers well even if i define it as strip layer with finite copper thickness. Please let me know if my analysis is correct.

[BigBoss]

Why did you select GND as slot ? Can you post the substrate illustration picture here ??

[volker@muehlhaus]

and circuit simulation with "TL-multilayer"

Can you show a screenshot of your schematic model? Schematic models couple to each other only through the circuit nodes, I wonder if that is realistic for your layout.

[pragash]

Why did you select GND as slot ? Can you post the substrate illustration picture here ??

the strip will consume a substantial amount of simulation time. converting GND layer to slot save simulation time without sacrificing the accuracy.

- - - Updated - - -

Can you show a screenshot of your schematic model? Schematic models couple to each other only through the circuit nodes, I wonder if that is realistic for your layout.

attached here. how do check circuit nodes?

[volker@muehlhaus]

attached here. how do check circuit nodes?

I meant the schematic models (circuit simulation). You write that it doesn't agree to EM, so I wonder how you modelled this in circuit simulation (what models and values).

One possibly related issue: From what I remember, you had used MSUB parameters with almost perfect conductivity in a previous discussion.

[vfone]

Any particular reason why did you use at one end of the inductor VIAS almost 3 times bigger than the VIAS on the other end?
Because they are in series, the DC current through all of them is the same, so will not help much (for this reason) to make bigger only some of them.

[pragash]

Any particular reason why did you use at one end of the inductor VIAS almost 3 times bigger than the VIAS on the other end?
Because they are in series, the DC current through all of them is the same, so will not help much (for this reason) to make bigger only some of them.

i used bigger ground vias to not to introduce additional inductance. i couldn't make the other side inductor bigger due to RF trace constraint.