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delay of inverters in series

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Sambhav_1

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HI
I am facing an issue during postlayout simulation where a chain of four inverters is there i have to obtain a min. delay. But when i change the w/l of the transistors there is no change in the delay, it is neither increasing nor decreasing. In prelayout simulation i can easily see the variation in delay while varying the w/l.
Any explanation for this behaviour in post layout simulation ?

i am working on 28nm.
 

Post-layout would have the transistors' W, L set by
the layout realities - are they made variable in the
netlist, or are you changing variables that do nothing?
 

dick_freebird said:
Post-layout would have the transistors' W, L set by
the layout realities - are they made variable in the
netlist, or are you changing variables that do nothing?
Click to expand...

if you mean by w/l as variable, then NO.w/l of each inverter is kept same. and when i am changin the w/l of the inverter ,there is no change.
 

I mean that in schematics W and L are often left as
variables but an extracted netlist only represents what
was laid out, and any variables from a reused schematic
based testbench might do nothing as a result.
 

Akshaay said:
HI
I am facing an issue during postlayout simulation where a chain of four inverters is there i have to obtain a min. delay. But when i change the w/l of the transistors there is no change in the delay, it is neither increasing nor decreasing. In prelayout simulation i can easily see the variation in delay while varying the w/l.
Any explanation for this behaviour in post layout simulation ?

i am working on 28nm.
Click to expand...

Maybe your metal RC is too worst and become the dominant.
But you mentioned no change in the delay, is it totally no change or the change is very minimum?
If totally no change, then I believe the way you hack your netlist is not correct.
 

dick_freebird said:
I mean that in schematics W and L are often left as
variables but an extracted netlist only represents what
was laid out, and any variables from a reused schematic
based testbench might do nothing as a result.
Click to expand...

no, i haven't left w and l as variables un schematic.
And i have extracted the netlist in same way i extract it before.
 

Reading this discussion I feel lost.
Could you please explain what would you like to achieve? What are the simulation conditions? Are the simulation differences occurs when comparing schematic level with extraction without parasitic?
 

Hi dominik
I want a certain delay using these inverters , but during pre-layout simulation i can see the variation of delay with w and l. But in post layout ,there is no change is seen by varying the w and l. Layout is also right , now i can only change placement and routing. I am unable figure out the problem.
 

I believe in the layout, transistors has fixed dimensions. So, to vary them you would need to make on-fly modification of the netlist.

You didn't provide any information about tools and methodology which you are using.
 

Dominik Przyborowski said:
I believe in the layout, transistors has fixed dimensions. So, to vary them you would need to make on-fly modification of the netlist.

You didn't provide any information about tools and methodology which you are using.
Click to expand...

"on-fly modification of the netlist" Can you elaborate on this ,what is it?
 

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