Sambhav_1
Full Member level 2
HI
I am facing an issue during postlayout simulation where a chain of four inverters is there i have to obtain a min. delay. But when i change the w/l of the transistors there is no change in the delay, it is neither increasing nor decreasing. In prelayout simulation i can easily see the variation in delay while varying the w/l.
Any explanation for this behaviour in post layout simulation ?
i am working on 28nm.
I am facing an issue during postlayout simulation where a chain of four inverters is there i have to obtain a min. delay. But when i change the w/l of the transistors there is no change in the delay, it is neither increasing nor decreasing. In prelayout simulation i can easily see the variation in delay while varying the w/l.
Any explanation for this behaviour in post layout simulation ?
i am working on 28nm.