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MOS capacitor when Vgs is -ve

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venn_ng

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I have a question on what happens to MOS capacitance Cgs+Cgd, when Vgs goes negative in the NMOS shown. I see that when Vgs goes negative, the channel is full of holes because of p- substrate, which means we see the Cox capacitance (without any other capacitance in series), but I am not sure if this is between Cgs (or Cgd) or Cgb. My intuition says it's between Cgb, but if that's the case, then there is no capacitance between Cgs (or Cgd), ignoring the overlap capacitance.
Attached the figure

mos_cap_negative.JPG

Thanks in advance
 

Get a C-V curve of the capacitor species in question.
There will be a "null" at the depletion range, higher in
both accumulation and inversion ranges. "How negative"
matters, as does whether it's N or P type and how high
the body (& gate) doping.
 

dick_freebird said:
Get a C-V curve of the capacitor species in question.
There will be a "null" at the depletion range, higher in
both accumulation and inversion ranges. "How negative"
matters, as does whether it's N or P type and how high
the body (& gate) doping.
Click to expand...

Thanks for the reply. My question is more generic. Is the capacitance formed between gate and bulk or is it formed between gate & source/drain when Vgs is negative?
 

Again, this varies with -how- negative.

Depletion region capacitance is lowest because the Tox
capacitance lies in series with the depletion capacitance
below the gate, to the body.

Accumulation capacitance is to the body (enhanced) by
way of the body contact.

Inversion capacitance is to the S/D terminals via the
channel charge sheet.

Negative for NMOS, negative for PMOS, put you in two
different regions (accumulation for NMOS, inversion for
PMOS).
 

Hi,

Thanks for the reply. In the case of accumulation region (shown in the diagram before), though there is a channel (of holes), S/D are n+ type so they are void of holes and have electrons, I still don't get how you could have a capacitance between Gate and Source/Drain when you are in accumulation mode. Though I could see a direct Cox capacitance between Gate & Bulk.
 

Usually, accumulation layer formed by holes (in nMOS transistor) is not called a "channel" - a channel is something that allows a current flow between source and drain.

When AC signal is applied to the gate, capacitive current for an MOS transistor in accumulation region will flow mostly to the bulk, so gate capacitance will be determined (mostly) by Cgb - gate to bulk / substrate capacitance.
There may be some capacitive current flowing form the gate to source / drain - through overlap capacitance, or gate to source/drain contact capacitance (high in scaled technologies, and especially - in FinFETs!), or through bulk-to-source/drain capacitance.
So Cgd and Cgs, while being lower than in inversion region, are not zero.
 

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