FFT plot of CT-Delta Sigma ADC which cannot be explained

Hello all,

I am designing a CT-Delta Sigma ADC. The spec of this ADC is:

3rd-order, 4-bit Quantizer, Fs=320MHz, OSR=16, BW=10MHz, CIFF structure

The problem I encountered is some strange result from the FFT of the ADC. Attached figure is 5 different input bin; from low frequency to high frequency, with two different condition. One is with an ideal feedback current DAC which is generated from Verilog-A model, and the other one is with the current DAC in transistor level. Other block of the ADC in these two condition are all in transistor level.

I cannot explain and find out the reason that cause the noise floor getting high and even becoming flat or some strange ringing. 1 input which is bin=79 has the same result for both condition.

The attached result is from Spectre. I have tried Hspice, but the results are similar. The setting of Spectre transient that I use is:
moderate, gear2only, ++aps
FFT window is blackmanharris

I have already improve my current DAC but the results remain same. I don't know whether this is still the linearity problem of main feedback current DAC or not.
Hope anyone can give me some advice, I will be really appreciate!!

Simon_Chueh said:

I cannot explain and find out the reason that cause the noise floor getting high and even becoming flat or some strange ringing.
1 input which is bin=79 has the same result for both condition.

Click to expand...

Loop is unstable except for bin=79 when you use transistor level feedback DAC.

Do you compensate excessive delay ?

Try to decrease amplitude of input signal.

pancho_hideboo said:

Loop is unstable except for bin=79 when you use transistor level feedback DAC.

Click to expand...

If it is the stability probelm, why only in-band noise is different? High frequency noise remain same. I ruled out the problem of loop-filter due to these reasons; however, I am not 100% sure about it.

pancho_hideboo said:

Do you compensate excessive delay ?

Click to expand...

Yes, I do compensate ELD. ELD is set to be half of clock cycle, which is realized by D-flip flop.

pancho_hideboo said:

Try to decrease amplitude of input signal.

Click to expand...

I have check the output of loop-filter, and I didn't see the overloading of quantizer happened. I forgot to put one case which is input amp=0, which I attach in this reply. The problem still remain, so I guess signal overloading is not the issue.

- - - Updated - - -

Hello all,

I compare current output of ideal DAC and transistor-level DAC, finding out that the error of transistor-level DAC is signal dependent. Maybe this is the issue?
I really don't know hot to check if a 4-bit DAC's linearity is 12-bit or not..., so it is difficult for me to design the current DAC.
(blue line: ideal DAC; red line: transistor-level DAC)

Simon_Chueh said:

I compare current output of ideal DAC and transistor-level DAC, finding out that the error of transistor-level DAC is signal dependent.
Maybe this is the issue?
.........................................................................
(blue line: ideal DAC; red line: transistor-level DAC)

Click to expand...

Glitch noise in red line causes in band floor up.

There is no inter symbol interference in blue line.
On the other hand, inter symbol interference exist due to glitch in red line.