DFT issues on scan clock input as "x"

Hi,
I'm learning DFT and trying to finish my design with DFT compiler. After I run command "dft_drc" in DesignCompiler, I found thousands of warnings on clock as "Clock input CP of DFF xxx was not controlled. (D1-1)". I tried to debug this with design vision to find that the clock input CP is marked as "x", which I think should be a toggle clock. I attached this screenshot. Can anybody help to understand what's wrong with my setting? why this clock input is set as "x"? thanks.

skyworld_cy said:

Hi,
I'm learning DFT and trying to finish my design with DFT compiler. After I run command "dft_drc" in DesignCompiler, I found thousands of warnings on clock as "Clock input CP of DFF xxx was not controlled. (D1-1)". I tried to debug this with design vision to find that the clock input CP is marked as "x", which I think should be a toggle clock. I attached this screenshot. Can anybody help to understand what's wrong with my setting? why this clock input is set as "x"? thanks.

View attachment 151044

Click to expand...

you have clock gating in there. it appears the other inputs of the clock gate instance are not connected, which makes the clock go X.

ThisIsNotSam said:

you have clock gating in there. it appears the other inputs of the clock gate instance are not connected, which makes the clock go X.

Click to expand...

Hi,
I just confused. If the gate cell gated the clock input, why the buffer input which connects to input port (pma5ck), is also "x"? I set this port as scan clock input port in script:

set_dft_signal -view existing_dft -type ScanClock -port [get_port pma5ck] -timing [list 45 55]


thanks.

skyworld_cy said:

Hi,
I just confused. If the gate cell gated the clock input, why the buffer input which connects to input port (pma5ck), is also "x"? I set this port as scan clock input port in script:

set_dft_signal -view existing_dft -type ScanClock -port [get_port pma5ck] -timing [list 45 55]


thanks.

Click to expand...

that I don't know. there are many reasons why a simulation can show only Xs, it might not even be related to DFT. are you experienced with gate level simulations? can you make the same circuit work under functional mode?

ThisIsNotSam said:

that I don't know. there are many reasons why a simulation can show only Xs, it might not even be related to DFT. are you experienced with gate level simulations? can you make the same circuit work under functional mode?

Click to expand...

Hi,
this is a synthesis process with DFT insertion, which I don't think it is a simulation. I just use design vision to trace why dft_drc reports these warnings. The input scan clock becomes to be "x", which I think should be a clue, but I don't know why. That is the reason why I come here for help;-)

skyworld_cy said:

Hi,
this is a synthesis process with DFT insertion, which I don't think it is a simulation. I just use design vision to trace why dft_drc reports these warnings. The input scan clock becomes to be "x", which I think should be a clue, but I don't know why. That is the reason why I come here for help;-)

Click to expand...

I see. Disregard my comment.