Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Minimum propagation delay of a cmos inverter

Status
Not open for further replies.
S

Sambhav_1

Full Member level 2
Joined
Jul 13, 2018
Messages
125
Helped
1
Reputation
2
Reaction score
3
Trophy points
18
Activity points
941
hi
How can i determine the min. delay of a cmos inverter if my if i know the min. and max. w and l of the transistors.
 

You have to know the minimum load capacitance too. Hard to estimate a real case, depends on wire length, minimum load gate numbers for example.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top