Slew rate for folded OPAMP with driver

Hello friends

Please I need the slew rate expresion formula for the circuit of OPAMP shown in the image,

Thank you very much

Like always, the slew rate δV/δt = Iout/Cout .

The current Iout of the output buffer is the adjusted current Ipre of the pre-amp stage (through M12, M10 ...) times the current gain by the W/L ratio(s) between the output- and pre-amp-stage Iout/Ipre = (W/L(MON))/(W/L(M10)) , or the ratio of the corresponding p-channel transistors - if different, take the smaller one for the Iout calculation.

Cout, self-evident, is the load capacitance Cload, plus the feedback capacitance (= compensation cap, in your case) times this gain factor (if different for p- and n-channel, take the bigger one, in this case).

Dear Erikl

Thank you very much for your reply,

Actually I am little confused, because you are mentioning the load capacitor in the calculation.... but if I understand it this way, I would say that for my Op-Amp the slew rate is not limited to the external capacitor, it is limited to the compensation capacitor as I can get confirmed by my simulation.

for my circuit, I am designing the floating current source of 50 uA and my compensation capacitor is 0.64 PF. if I would use the equation δV/δt = Iout/Cout = 50uA/0.64 PF it should give me Slew rate = 78 V/uS. However I am getting in my simulation only 48 V/uS.

Please correct me if I am wrong and thank you once again.

The class-AB output stage should handle the high charge-up current of the load capacitor, you can check it easily by comparing with or without load capacitor (the slew-rate).
I think you are right when you calculate only with the compensation capacitor, because the 1st stage of your OPAmp will see only that and those current is limited by the preamplifier.
48V/us is quite close to your expected 78V/us, don't trust in Spice level 1 equations for different parameters. These are useful to estimate things but the simulation of BSIM3,BSIM4 level devices will give you much accurate answer.
Possible reasons of difference could be:
1, you are using non-linear compensation capacitor
2, the 1st stage current sources are not exactly 50uA biased
3, wrong formula...I haven't checked it analytically...

Dear frankrose,

Thank you for your comment,

So me and you are agreed with the point that the slew rate is limited to the pre-amplifieer, as the output amplifier can sufficiently drive the external capacitor,

I would only answer one of your points, I am not using spice level one in my simulation, I am using the BSIM3 or BISM4 modules.

I am just thinking of one thing, if you look back to the figure you see where the compensation capacitor is inserted, may be it helps,,

Junus2012 said:

... δV/δt = Iout/Cout = 50uA/0.64 PF it should give me Slew rate = 78 V/uS.
However I am getting in my simulation only 48 V/uS.

Click to expand...

I think you must consider the output capacitance of the driving node (the output), too, in parallel. You could try it by adding a cap (to GND).
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BTW: Pls. adhere to the official lower case for the abbreviation of pico (pF) and of second, here V/µs .
V/µS means Volt per microSiemens, which would end up in V²/µA :evil:

Dear Erikl,,

Thank you once again,

The problem is that I need to write the equation in my work, and therefore I need the mathematical expression for the slew rate.
Second thing please, I can design the floating current source with any value, in the book of Jakob he is designing it to be half of the tail current of the differential pairs, so I just want to know for this circuit is there rule for this amount.
In normal folded cascode circuit we usually bias the folded transistor with a current equal to the tail current and that is obvious why, but with folded using floating source with up and down mirror like this circuit I see I can select any value. is it right?

The other question why this man is using only one compensation capacitor, every one is using two, one for the upper driving transistor and the other for the down one

Thank you once again

Junus2012 said:

The other question why this man is using only one compensation capacitor, every one is using two, one for the upper driving transistor and the other for the down one

Click to expand...

It uses one because it is in a book. Not the most practical, but not that is the point.
Others use 2 because in the pre-amplifier the bottom or top current mirrors can enter into triode region, not at the same time. So at output signal transition the response is better with 2 caps, because 1 of them will be always connected to a mirror which is in saturation.
Sometimes these caps are MOS varactors which C-V curve is non-linear. Imagine only 1 cap as on the figure above, and you can see that at low output voltage the compensation cap's value will drop. This can cause ringing at low output, but if you imagine the other cap too you can see the added cap has its highest value at low output voltage, so it can eliminate the ringing.

If you have a comp cap to the upper transistors you'll have the feed forward zero. In this configuration it is hardly a problem because you cab consider the source of the upper transistor as almost ac ground and thus the feed-forward action is greatly reduced but it is still there since that upper compensation is in the signal path. Not the case with the lower compensation capacitor.