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  1. #1
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    synthesized netlists simulation issue

    Tools: Synopsys design_vision 2013 / Questasim 10.0d / tech ST65nm

    I have several issues with simulation of my synthesized netlists from design_vision.
    1- As a simple design, I synthesized a generic multiplier. Behavioral simulations go well, simulation synthesized netlist, the simulator generates several intermediate values which I cannot figure out where from the come!!!

    As I mentioned this simple design, is purely combinatorial and simply implemented as:
    Code:
    entity MultBlock is
      port (
        MultWord1xDI : in  unsigned(WORDLEN_MEM/2-1 downto 0);
        MultWord2xDI : in  unsigned(WORDLEN_MEM/2-1 downto 0);
        MultOutxDO   : out unsigned(WORDLEN_MEM-1 downto 0)
        );
    end MultBlock;
    architecture rtl of MultBlock is
    begin
      MultOutxDO <= MultWord1xDI*MultWord2xDI;
    end rtl;
    Attachment 151014

    A snapshot of the simulator results is added? I tried to make a relation between the real input, midterms and final output investigating different options such as partial product, and, or ..., however no clue what are these values?
    Can anyone with experience in this issue help me to understand them, since I need to avoid any wrong result at anytime???

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  2. #2
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    Re: synthesized netlists simulation issue

    Hi,

    your attachment is invalid.

    There is a timeout.
    Donīt waste too much time from uploading_the_attachment to submit_your_post.

    Klaus
    Please donīt contact me via PM, because there is no time to respond to them. No friend requests. Thank you.



  3. #3
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    Re: synthesized netlists simulation issue

    Hi
    I tried to post the image inline with the message, probably something went wrong.
    I attached the image again to this reply.
    BR



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  4. #4
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    Re: synthesized netlists simulation issue

    The different values show up due to the various different combonational paths of the logic arriving to the output at different times due to more cell delay in one path compared to another.



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    Re: synthesized netlists simulation issue

    just simulate long enough with a stable input and you will see a stable output. that's how combinational logic works, there is nothing wrong here.
    Really, I am not Sam.



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    Re: synthesized netlists simulation issue

    Quote Originally Posted by ads-ee View Post
    The different values show up due to the various different combonational paths of the logic arriving to the output at different times due to more cell delay in one path compared to another.
    Thanks for your reply.
    I am wondering how this effect can be avoided, meaning in synthesis flow how I can control the paths somehow to avoid receiving some invalid midterms. To my specific design application, any wrong or invalid output value is a killer (as long as the output port is stable and giving a value out, this value is taken and been processed on the fly)
    I actually simulated it in for a long period. Also added a delay to my testbench for emulating the setup and hold time (for another case with registers in the design)
    Any hint is appreciated!



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    Re: synthesized netlists simulation issue

    Quote Originally Posted by manpmanp View Post
    I am wondering how this effect can be avoided, meaning in synthesis flow how I can control the paths somehow to avoid receiving some invalid midterms.
    You can't, that is not how combinational logic works. Glitches will happen and are completely expected. You need a flop to prevent these 'glitches' from moving further down.
    Really, I am not Sam.



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