Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Innovus routing and floorplanning with analog components netlist generation

Status
Not open for further replies.

EEPuppyPuppy

Junior Member level 3
Joined
Jun 14, 2018
Messages
26
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
343
I have used Virtuoso to do the sketchmatic and layout of my oscillator and other components using TSMC 65nm CMOS transistors. Now I am trying to put my components and any other TSMC 65nm components together to build a large circuit for tapeout. So I need Innovus to do the physical design.
It seems like most of the tutorials online use the netlist generated by Verilog (.v file) to import the netlist into Innovus. Since some of my components are not digital, I might not be able to use Verilog.
Could anyone help me regarding the issue that how to generate the netlist file in my case?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top