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6th February 2019, 13:02 #1
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How to make a better design for this SMPS post regulator filter circuit?
For minimizing SMPS ripple and especially noise, I’m trying to make a small interface which is a post regulator cascaded after an LC filter. I have come across some papers related to this topic and the idea is to establish good noise rejection by using a low drop out LDO regulator for frequencies lower than like 100 kHz and for higher frequencies by using an LC filter. At this video it also gives a very nice example at around 2:56.
The topology can be seen in the circuit I have drawn in LTspice. Here is my circuit in question(the one inside the dashed box is the filter):
The circuit is set for 120mA load with 12V regulator output to a 15V input.
Now my biggest problem in simulation was that since I don't know the DC output resistance R3 of an SMPS and it can be different for any different SMPS. So for the worst case I took it as 0.02 Ohm. I say worst case because for the LC filter this doesn’t prevent the resonance problem. So to prevent the LC resonance, I added a parallel 1 Ohm resistor R1 with the inductor L1. In simulation L1 and C2 forms a very nice high freq. filter. Then I use this LT1086 as an LDO. Here is its datasheet and in applications it is mentioned that it is also recommended for SMPS switching noise filtering(it says "Post Regulators for Switching Supplies"). R2 and Rp set the output to around 12V for a 15V input. Rp can be a potentiometer to finetune the output voltage. According to the datasheet if I’m not mistaken the C1 is needed to be a tantalum capacitor and C3 is a ceramic capacitor both with low ESR.
Now I have made transient analysis in LTspice for this filter where the input is 15VDC with 1V pulse noise (with 10p rising falling edges) superimposed on it. So I repeated the same procedure for different noise pulse frequencies 50Hz, 100Hz, 1kHz, 100kHz, 1MegHz.
Below are the simulation results for input and output for these frequencies:
At 50Hz:
At 100Hz:
At 1kHz:
At 100kHz:
At 1MegHz:
The results are peak to peak amplitudes at the output for 1V pulse input noise at different frequencies. And here are the results for each:
50Hz > 1.6mV
100Hz > 3.8mV
1kHz > 173uV
100kHz > 41uV
1MegHz > 1uV
Here is the power dissipation for the regulator which is around 0.5W:
And finally here below is the current drawn from the SMPS and flow through input stage:
My questions are:
How can I reduce this supply current? Apparently it is 6A. Obviously there is something wrong with this even though the filtering is fine.
I would be glad to hear any other recommendations for this circuit. SMSP cannot handle more than 500mA or maybe 1A, so reducing C2 can be an option but that degrades the filtering. Or am I exaggerating the 1V noise?Last edited by doncarlosalbatros; 6th February 2019 at 13:30.

6th February 2019, 13:41 #2
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Re: How to make a better design for this SMPS post regulator filter circuit?
How can I reduce this supply current? Apparently it is 6A.

6th February 2019, 13:59 #3
Re: How to make a better design for this SMPS post regulator filter circuit?
Hi,
There's a lot I couldn't answer, I'm afraid. Regarding the 6A supply current, do you add internal resistance to the power supplies? Adding a little might help, especially if you're fortunate enough to know the actual source resistance of the supplies (in simulations, I just put a highly questionable 0.5R on them all due to ignorance of the realities of figuring out battery or supply resistances).

6th February 2019, 14:05 #4
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Re: How to make a better design for this SMPS post regulator filter circuit?
Do you mean 1V is too much and non realistic? What value would be a good estimate?
Do you also have any other recommendation for this circuit or component values? Do I need parallel caps for C2 to reduce ESR?
Can the reg handle 0.5W continuous without any heat sink?
Thnak you
   Updated   
Yes R3 represents the output resistance of the supply which I chose 0.02 Ohm.
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6th February 2019, 14:21 #5
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Re: How to make a better design for this SMPS post regulator filter circuit?
Hi, The output impedance of an SMPS is not a constant value. It is frequency dependent.
You can measure it by supplying a current wiggle to at the output of your SMPS and obtaining the frequency response curve of the output voltage. The maximum value is usually around the crossover frequency though.
Even a good simulation can tell you a close value.
Actually, you won't get Zout=20mOhm unless your SMPS is "properly" designed.
Akanimo.

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6th February 2019, 14:24 #6
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6th February 2019, 14:33 #7
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Re: How to make a better design for this SMPS post regulator filter circuit?
The 6A peak inductor current that you are showing us is at about 66.7 Hz. Why that frequency?
Last edited by Akanimo; 6th February 2019 at 14:54.

Akanimo.

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6th February 2019, 14:41 #8
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Re: How to make a better design for this SMPS post regulator filter circuit?
Hi,
It is just the worst case for the current for low frequency. Maybe it is not realistic.?
It could be a 50Hz noise I thought.
Please let me know if you think I need to change anything for the way of thinking or components.
This is why I asked here I might have been wrong in way of modelling also design.
I appreciate your answers.

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6th February 2019, 14:49 #9
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Re: How to make a better design for this SMPS post regulator filter circuit?
Because you are asking this, if you actually designed the SMPS, then I'd say estimate Zout at 250mOhm.

Akanimo.

6th February 2019, 14:53 #10
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Re: How to make a better design for this SMPS post regulator filter circuit?
Here is an example of SMPS datasheet I use(they dont write about Zout explicitly). Here is the datasheet of it https://docsemea.rsonline.com/webd...6b8129224d.pdf 15V model.
Maybe theres a way to estimate the Zout from the given parameter values but I dont know how.

6th February 2019, 15:05 #11
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Re: How to make a better design for this SMPS post regulator filter circuit?
Wait, what is the current rating of the SMPS?

Akanimo.

6th February 2019, 15:18 #12
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6th February 2019, 16:52 #13
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Re: How to make a better design for this SMPS post regulator filter circuit?
I'm beginning to think that you should remodel the SMPS such that you can't get more than the rated output current from the SMPS.

Akanimo.

6th February 2019, 18:49 #14
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Re: How to make a better design for this SMPS post regulator filter circuit?
Resonance close to 100 Hz. Therefore a low impadance is presented @ 100 Hz resulting in high current.
Current waveform presented by LTSpice @ 100Hz is expected due to resonance of the LC filter elements. My hand calculation gives me a peak current of (4*0.5/Pi)/0.121~5.26 A
Impedance seen by the "Voltage source" @100Hz ~0.121 ohms.
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7th February 2019, 02:26 #15
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Re: How to make a better design for this SMPS post regulator filter circuit?
Hi CataM,
Very much correct.
Current waveform presented by LTSpice @ 100Hz is expected due to resonance of the LC filter elements. My hand calculation gives me a peak current of (4*0.5/Pi)/0.121~5.26 A
Impedance seen by the "Voltage source" @100Hz ~0.121 ohms.
The SMPS here is rated between 0.5A to 1A according to the OP. How do you translate that to obtaining 5.26A? 5.26A has an average value significantly higher than 1A. If this were to be the case, then the SMPS would likely become unstable.Last edited by Akanimo; 7th February 2019 at 02:51.

Akanimo.

7th February 2019, 14:17 #16
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Re: How to make a better design for this SMPS post regulator filter circuit?
Hello all,
I came across this document https://www.maximintegrated.com/en/a...dex.mvp/id/883
The third option in document cascading two regulators. But I also saw designs using common mode chokes or ferrite beads.
There are many topologies. Does anybody have idea in my case would be more suitable?
My SMPSs are 12V or 24V the currents are between 500mA to 1A.
Thanks

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7th February 2019, 19:14 #17
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Re: How to make a better design for this SMPS post regulator filter circuit?
Filter impedance, the only thing post #1's waveforms can do.
The SMPS here is rated between 0.5A to 1A according to the OP. How do you translate that to obtaining 5.26A?
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8th February 2019, 08:56 #18
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Re: How to make a better design for this SMPS post regulator filter circuit?
With this I can safely conclude that you know the exact value of the OP's SMPS output impedance. Please give the OP that figure. The OP wants to use it in simulation.
Also please help in modeling the SMPS too so the OP can get a solution and forum members can learn from it.
Thanks in anticipation.
Akanimo.

8th February 2019, 12:29 #19
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Re: How to make a better design for this SMPS post regulator filter circuit?
With the wrong load, you will burn it and that is it.. unless it is current limited.

8th February 2019, 21:13 #20
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Re: How to make a better design for this SMPS post regulator filter circuit?
With this I can safely conclude that you know the exact value of the OP's SMPS output impedance.
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