Shielding in IC analog layout design

Hi.Could you please say to me,what can be the differences,when we are shielding the signal net with VDD or VSS in IC layout design.For example the analog signal from clock.

Each net carries its own noise actors, they may be opposite
in action (like, Vdd glitches from switching circuitry will be
low-going while Vss glitches, positive-going). The bond wire
inductance (or balls / bumps, lesser but finite) and close-in
PCB traces all turn dI/dt into voltage impulses. Without an
idea about the larger network, power and signal integrity,
you can't say one or the other would be "more effective"
or that either would be effective at all. You would like
to know the character of the nastiness already on each
trace, before deciding which one you ought to "couple to"
in an attempt to reduce "noise". Like, you might get more
than you bargained for.

"Shielding what, from what?" is the other end of it. Are
you seeing E-field coupling? Maybe shielding works. Is it
H-field (like longitudinal current in an "aggressor" trace
inducing some, in a long-parallel-run-length "victim"?
Then you're pretty well hosed, because you can't "shield"
magnetic fields with on-chip materials.

Running differential clocks can mitigate the far-field coupling
and routing them "twisted pair style" can bring "far" closer.
At the cost of -at least- 2X clock power (likely worse
you are deliberately coupling antiphase signals at low spacing).
But "shielding" a single ended clock will also take power from
the driver, push it into the ground (perhaps polluting it from
another bit of circuit's perspective - you trade "radiated"
for "conductive" coupling, to an imperfect ground or power
net that -will- be perturbed. You might try to model the
behavior to assess sensitivity of blocks to rail noise, and to
quantify that rail noise, to inform your decision.

Green_Ic said:

Hi.Could you please say to me,what can be the differences,when we are shielding the signal net with VDD or VSS in IC layout design.For example the analog signal from clock.

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Normally I will shield it with vss as vss has stronger power grid.
Some proposed to shield with 1 side Vdd and another side with Vss to reduce dcd