Verification for VHDL keeping FPGA in mind

I am still writing complex self-checking test-benches in VHDL-2008 to exercise my DUT. I would like to move to some Opensource Verification methodology.

Two of them I came across are OSVVM and UVVM. I would need suggestions as to which one would be better to stick to.

UVVM has been released after OSVVM and Bitvis summaries its advantages here:
http://bitvis.no/dev-tools/uvvm/

One thing that is bugging me is the Supported simulators for Bitvis UVVM - "Vivado: Awaiting proper VHDL 2008 support" (I am mostly using Vivado simu).
Anyone knows how-much of hindrance Vivado 2018.3 brings in for UVVM implementation (it is known that Vivado does not support all of VHDL2008)?

The problem for Vivado is it's lack of 2008 support. It has nothing to do directly with UVVM and OSVVM. But both of them use a lot of the 2008 features.
You'll get full OSVVM and UVVM support from any simulator that has proper 2008 support, which is just about everyone else.

I am fully on board with OSVVM. IMO, its like a tool box where you can pick and chose which bits to use at any time. So its very flexible in how you use it. You could quite easily take an existing testbench and OSVVMify it a little at a time.
On the other hand, UVVM feels like an entire framework. You have to conform to the way UVVM does things, so you would likely need to start existing tests from scratch using the UVVM framework. This is why Ive decided not to invest time in it.

Also note that you dont have to use one or the other. It would be perfectly fine to use OSVVM features inside a UVVM testbench. UVVM even used to ship with OSVVM (they now ask you to get it separately I think).

IMO, UVVM is an attempt to have a go at UVM in VHDL. If you really wanted UVM, why not use UVM?

The Cynic in you should also flag that both methods were developed by training companies - Synthworks was OSVVM (Owned by Jim Lewis, the guy who leads the VHDL LRM) and BitVis. They both sell training in their respective methodologies.

I currently have a AXI4 (full AXI4, not just lite, although I havent implemented all the features or Assertions) VIP suit that uses OSVVM for randomisation and scoreboarding. (All written in VHDL, and runs very fast in ActiveHDL)

Thanks a lot for your comments and suggestions.

IMO, UVVM is an attempt to have a go at UVM in VHDL. If you really wanted UVM, why not use UVM?

Click to expand...

I am still exploring and have to make a decision.

Maybe I will try to change my current TB on the lines of UVVM and see how much of an effort that it. It should also show me how much of a restriction Vivado brings in.

dpaul said:

Thanks a lot for your comments and suggestions.


I am still exploring and have to make a decision.

Maybe I will try to change my current TB on the lines of UVVM and see how much of an effort that it. It should also show me how much of a restriction Vivado brings in.

Click to expand...

I think Vivado has an issue where the simulator 2008 support actually lags synthesis support. Specifically unconstrained record types. This may be a real blocker.
I only use vivado for synthesis (currently locked to 2018.2). I dont bother with the simulator.

Intel provide modelsim for free.