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Optimize shifter synthesis in Design Compiler

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oAwad

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I'm using Design Compiler to synthesize a simple arithmetic right shifter in verilog
Code: 
out = in >>> shift
"shift" is 5-bits, but I know the max. value "shift" can get is 17 so I don't need the whole 32-bit shifter. How to instruct Design Compiler to synthesize the shifter as just a 17-bit shifter?

Thanks
 

Make an intermediary variable called shift_lim that’s limited to 17 and use that instead.

Also note that the size of in and out will also limit the size of the shifter.
 

asdf44 said:
Make an intermediary variable called shift_lim that’s limited to 17 and use that instead.
Click to expand...
how can I create a variable that's limited to 17?
asdf44 said:
Also note that the size of in and out will also limit the size of the shifter.
Click to expand...
yes sure, but my concern is the "shift" signal, since it controls the levels of the barrel shifter.

Thanks
 

wire [4:0] shift_lim = (shift > 5’d17) ? 5’d17 : shift;

Admittedly this requires some intelligence in the synthesizer to understand how to optimize it but my understanding is that a modern synthesizer can do it. You could check the schematic to see exactly what it did.


Another fallback is a 17 case case statement explicitly handling the 17 possible shifts.
 
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