oAwad
Full Member level 2
I'm using Design Compiler to synthesize a simple arithmetic right shifter in verilog
"shift" is 5-bits, but I know the max. value "shift" can get is 17 so I don't need the whole 32-bit shifter. How to instruct Design Compiler to synthesize the shifter as just a 17-bit shifter?
Thanks
Code:
out = in >>> shift
Thanks