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Response of CMOS inveter in parallel

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Sambhav_1

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Hi folks,
I want to know about the response of the 2 CMOS inverters connected in parallel (i.e sharing the same input and outputs are connected) when:
1. Both inverters are identical.
2. Second inverter is having its PMOS and NMOS dimensions multiplied by some factor.

How would the output response will change in (1) these two cases (2) Comparison to a response of single inverter?
 

From reading Forrest Mims notebooks it appears okay to parallel several invert-gates if they are in the same chip (example, cmos hex inverter 4049 or 4069).
Each gate supplements a few more mA to load capability.
All gates transitions at half the supply V.
All gates are fed from the same supply V and ground wire.

I don't know enough about wafer fabrication to reply about your second situation.
 

Akshaay said:
Hi folks,
I want to know about the response of the 2 CMOS inverters connected in parallel (i.e sharing the same input and outputs are connected) when:
1. Both inverters are identical.
2. Second inverter is having its PMOS and NMOS dimensions multiplied by some factor.

How would the output response will change in (1) these two cases (2) Comparison to a response of single inverter?
Click to expand...

If it is parallel and everything is indentical, it would just like you are sizing them 2x.
But in real world, if you are putting 2 inverters, the input loading/output loading will never be identical. This will cause pulse reaching each of the inverter are different and cause potential crowbar current.
 

If the transistors are on the same chip but different is size, then it's likely that the two inverters will have slightly different switching times, leading to a shoot-through current spike during logic transitions.
 

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