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compensation folded OPAMP with nulling resistor or transistor

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Junus2012

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Hello,

I finished with the design of this folded operational amplifier, I am compensating it by using only capacitors as shown in the figure,

I found some people where they add resistor or transistor in series with the compensation capacitors,

could you please tell me what is the difference in this case and what are the rules I should use to design this resistor or transistor.

Thank you very much folded.png
 

Resistor is used to shift the frequency of the right half-plane zero (RHPZ) to higher values, or to place RHPZ onto the left half plane.
Details: **broken link removed**

Above circuit doesn't require shifting resistor because the capacitor is connected to a low impedance node, to a cascode transistor source. This is called "Ahuja-compensation".
Details (page 10-11):**broken link removed**
 
Thank you frankrose for your nice answer,

now I would like to ask you other question related to it,

when the above configuration doesnt require resistor, why some people connect the capacitor to the gate of the output transistor (MOP and MON) and then they use to connect resistor or transistor working as a resistor,

in my opinion and after your answer the circuit in the image is better because it simplify the compensation.

thank you once again
 

Miller compensation is the fundamental method, always can work, Ahuja compensation is invented later. Designers learn Miller probably first, and actually other is not necessary. I can imagine these simple reasons but I don't know. And Miller is availabe in higher percentage of low-voltage circuits I think, because Ahuja requires cascode device in the 1st stage, extra bias circuit + consumption, so not simplier.
I would say the performance is better than Miller rather, but the trade-off between area/speed/consumption is application dependent.
 
Ahuja compensation is not necessarily better nor simpler. It may cause bad peaking in you loop gain and hence stability issues in the closed loop opamp. The reason is that there is an extra loop in the circuit - drain of MON, capacitor, M10 and back to the gate of MON. This loop needs to be stable too and the zero that it introduces needs to be positioned correctly with respect to the unity cross-over frequency of the main open loop amplifier. Miller compensation doesn't have these problems. Yes, it introduces a RHP zero which can screw up with the PM of the loop gain but it is easily fixable by placing the series resistor. However, if Ahuja compensation is done right it can push the non-dominant pole to higher frequencies for the same compensation capacitor compared to Miller. Also, from another point of view, the amplifier can drive higher cap loads for the same compensation capacitor as used for Miller compensation but with lower cap loads.
 
...there is an extra loop in the circuit - drain of MON, capacitor, M10 and back to the gate of MON. This loop needs to be stable too and the zero that it introduces needs to be positioned correctly with respect to the unity cross-over frequency of the main open loop amplifier.

In Ahuja there is no feedforward path for the capacitor, because the source terminal of M10 has low voltage gain (virtual ground). Thus teoretically it doesn't create zero.

...the amplifier can drive higher cap loads for the same compensation capacitor as used for Miller compensation but with lower cap loads.

Hmm. What did you want to say here?
 
Actually, it does create a zero and this is a well known fact. This is not the feed-forward zero as in the Miller compensation because there is no feed-forward path here. Of course, if you assume that the input impedance of the cascode device M10 is 0, then no zero is there. But analog designers prefer to be more realistic than that. With the presence of 1/gm impedance at the source of M10 there is a high pass transfer form the amplifier output to that source node. However, this high pass function is in the feedback around the second stage. If that gm/C frequency of the high pass function happens to be after the second pole of the main amplifier, then the loop gain will have two poles before 0dB cross-over and will cause a lot of ringing.

Second part of your question - I think some kind of a typo happened there. The meaning should be that the higher cap loads could be driven for the same compensation capacitor compared to Miller.
 
Thank you guys for the interaction with my post,

I have simulated the circuit with normal miller configuration and it gave me less GBW comparing to the active proposed one by the image,,,

However that led me to other question.... am I still able to connect an impedance equal to 1/gmo with this toplogy ?

the second question what is the slew rate formula for this connection (of the circuit in the image) ?

thank you a lot
 

Slew rate should be similar to what you would have with Miller compensation.
 
Thank you suta, but I dont know which current i should use in the formula of the slew rate,,,, the tail current or the floating current ?

please give me the expression
 

If that gm/C frequency of the high pass function happens to be after the second pole of the main amplifier, then the loop gain will have two poles before 0dB cross-over and will cause a lot of ringing.

That zero never caused an issue for me as I remember, if it is well-known I think I am under-educated. But it doesn't seem unconditionally true the zero will cause ringing if it happens after the 2nd pole, if it happens between 1st and 2nd poles it looks dangerous too. We don't want to cancel the effect of the 1st pole, otherwise 2nd and 3rd pole will determine the loop characteristics. However, I haven't experienced that either.
 
Frankrose, maybe I'm not explaining clearly. So, I sketched something in the attached picture. This is for the stability of the local loop, not the external feedback loop. I kept the notations from the original post's picture. Hope it is clearer now.



Ahuja.PNG
 
I have attached a link about Ahuja above (page 10-11), there is a similar small-signal model, basically the same just with other cascode arrangement, that uses PMOS, nevermind. Which is more important that zero you mentioned is really there, however because of the increased 2nd pole frequency it is not even mentioned that would cause ringing, moreover it is described as a good thing to enhance the compensation in P.E.Allen's book. So it can be well-known, he wrote about it in more details in his book, even a pole-zero plot is available about the typical arrangement of the roots:

ph61y5em.png


Normally this zero is between the 1st and the 2nd pole, which is described above is not too good, can be bad, however you said:

If that gm/C frequency of the high pass function happens to be after the second pole of the main amplifier, then the loop gain will have two poles before 0dB cross-over and will cause a lot of ringing.

Does it a usual case when this zero happens after the multiplied 2nd pole? And does it usual that loop gain is still above 0dB at the multiplied 2nd pole too?

Hard to see me your sketch, I will analyse it further, but looks good, thank you for that.
 
There is a good paper about that type of compensation in Analog Integrated Circuits and Signal Processing: "Eliminating complex conjugate poles in two-stage operational amplifiers with current buffer Miller compensation". It kind of talks about this kind of things.
 
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