Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

2M multiplication method

Status
Not open for further replies.

promach

Advanced Member level 4
Joined
Feb 22, 2016
Messages
1,199
Helped
2
Reputation
4
Reaction score
5
Trophy points
1,318
Activity points
11,636
Have anyone used this 2M multiplication method ?

By trading a small factor of logN in the asymptotic area, the following algorithm gives a feasible and nicely regular silicon layout

1) How does the increase of logN in area complexity resulted in regular layout ?

2) Besides, adding those '2' (or two '1's in binary, just imagine putting 1'b1 on top of each other vertically) by itself also requires carry-save adders which may also contribute to the overall latency or delay as well as resulted in irregular layout ?

VcPzLFY.png


NaqjC6G.png
 
Last edited:

Most people now (and for many years) just use embedded multipliers. They are now cheap and plentiful.
What are you reasons you are investigating logic multipliers from many years ago?
 

For study purpose.

How exactly is the increase of logN area used for producing regular layout ?
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top