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Multiprocessor comunitacion USART in STM32Fxxx ?

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asrock70

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I looking for an example of use Multiprocessor comunitacion over USART with hw realisation.

I need to connect 4 MCUs on 4 boards, about 10cm between processors, speed 38400bps.
It looks simple, connect master TX with RX on slaves and RX on master with TX on slave,
but I would not like to find out that because of the parasitic bus capacities it does not work or is unreliable.
Likewise sw realization, slave is idle and comunicate only if addressed, but I'd rather see a sample solution.
Unfortunately I did not find anything in the confusing ST site.
 

Hi,

it´s not a problem of microprocessor.
It is a problem of
* bus topology (star, peer to peer, ring..)
* bus hardware, schematic (RS232, RS485, RS488, wired AND ... )
* protocol, including timing (Profibus, Modbus ...)

Klaus
 

The intended IO-standard is 3.3V CMOS with tri-stated slave TX drivers if I understand right. Bus capacitance is hardly a problem for short distance, it's easy to calculate signal rise times and relate it to bit duration, isn't it?

Common mode noise may be however a problem, depending on the system topology and environment. That's why people are using differential signaling (RS-485) or higher signal levels (RS-232, LIN bus etc.) in a noisy environment. Validating the transmission with CRC can also reduce the error rate.
 

OK I will specify the details.
Board is primary synchronous buck converter 1-40V / 0-25A switching frequency is over 220kHz with full ceramics input and output capacitor.
MCU over DAC set output U/I and over ADC control output U,I, temperature. etc.
The board can be connected in parallel as 100A current supply for galvanic plating.

For controll will be use master MCU or PC or any as Raspberry Pi.
Transmitted data very simple Set or Read voltage , current + 8bit CRC.
Will USART (TTL 3,3V level, on bus topology, lenght up to 50cm) work fine in such an environment?
 

Hi,

OK I will specify the details.
Board is primary synchronous buck converter 1-40V / 0-25A switching frequency is over 220kHz with full ceramics input and output capacitor.
MCU over DAC set output U/I and over ADC control output U,I, temperature. etc.
The board can be connected in parallel as 100A current supply for galvanic plating.

For controll will be use master MCU or PC or any as Raspberry Pi.
What has this to do with the communication?

Better tell about the (requested) bus informations.

Will USART (TTL 3,3V level, on bus topology, lenght up to 50cm) work fine in such an environment?
This seems you don´t want to use dedicated drivers....
* Tx(Master) to multiple Rx (slaves) is not the big problem
* but multiple Tx(slaves) to one Rx(Master) is a problem, because you can not connect multiple push-pull drivers as it causes short circuit currents.

Thus you need to decide how to solve the probelm.
* AND gates
* openCollector, openEmitter + pullup
* three state --> how is the high_impedance state controlled? Hardware, software...

What about
* protocol timing
* collision detect

Klaus
 

Will USART (TTL 3,3V level, on bus topology, lenght up to 50cm) work fine in such an environment?
Depend on many details, e.g. is the control circuit isolated from DC bus? Power electronics system is an environment where I would consider RS-485 transceivers with high common mode range instead of "TTL".
 

What has this to do with the communication?
With communication at first glance nothing, I mention this because of the specification of the environment and sources of interference.In other words on every board is flowing up 20A and is high current 220kHz switching source of interference, all board switching on synchronized clock.

This seems you don´t want to use dedicated drivers.
Yes, I prefer it, but I do not insist on it
I am primarily concerned with a simple, inexpensive and functional solution

My communication scheme is very simple.
Only one master can initiate communication.
Master adresses one or all slaves , if a response is required to address just a specific one slaves

STM32F USART have direct hw support for multiprocessor communication and have any support for 4/7 bit address wake up from idle.
The amount of data transmitted under 100bytes/s on each board, data is transferred to and from mater to slame not not between slaves.
 

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