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Wallace Tree Multiplier Questions

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promach

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1) Why "the number of multiplicand-multiples reduced from n to ABOUT 2n/3" ? How is this being done ?

2) What does it actually mean by "applying this principle about log(base = 3/2) of n times, the number can only be reduced to 2" ?

3) Why the overall delay is O(log n) ? Why does fast carry adder has O(log n) delay ?

4) Why 2-bit Booth recoding only reduce height of wallace tree by one or two level ? What about multiplier bit-pair encoding ?

5) Why does the author suggest to use larger counters instead of full adders ? To speed up the number of intermediate stages ?

6) Why is Wallace Tree circuit irregular in terms of layout and routing ?

7) How is a 4-2 adder helping to increase circuit regularity ?

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I have typo mistake in the previous post,

In question 3) it should be fast carry propagate adder instead of fast carry adder
 

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