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x snap spacing and y snap spacing

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student14

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Can someone help me iin identifying where I can check the x snap spacing and y snap spacing of silterra 130nm? I cant fnd in any document. Does anyone know the X snap and ysnap spacing of silterra 130nm for layout?
 

I don’t know what tool you use.
If you use Cadence Virtuoso as Design Framework,
open Layout>Options>Display Options
 
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I don’t know what tool you use.
If you use Cadence Virtuoso as Design Framework,
open Layout>Options>Display Options

Thanks for your reply. Yes I know this. I want to know what should be the X snap spacing and y snap spacing. What values should it be. I am using cadence silterra 130nm.
 

Set any value you like.
Really??? Can I use grid 0.0000001u?
If you not sure, don't tell so assured like that.

Thanks for your reply. Yes I know this. I want to know what should be the X snap spacing and y snap spacing. What values should it be. I am using cadence silterra 130nm.
For your question, you can found it in PDK document called PhysicalDesignRule.
It's specified in General Layout Requirement - Layout Grid part (I referenced in silterra180nm and supposed the same on silterra130nm).
I think the value is 0.005u.
 

Really??? Can I use grid 0.0000001u?
If you not sure, don't tell so assured like that.


For your question, you can found it in PDK document called PhysicalDesignRule.
It's specified in General Layout Requirement - Layout Grid part (I referenced in silterra180nm and supposed the same on silterra130nm).
I think the value is 0.005u.

I cant find the physical design rules. In the PDK documents I have only four files which is related to smart tool kits list of layers and reference manual which is not providing the design rules. Thats what the issue is. From where I can get it now?
 

Yes, as far as you don’t care about off-grid.

Set any value according to your need.

But I do have to care about grid, right? Because my layout is check with DRC desk and fabricated, I have to follow the rule from manufacturer, right?

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I cant find the physical design rules. In the PDK documents I have only four files which is related to smart tool kits list of layers and reference manual which is not providing the design rules. Thats what the issue is. From where I can get it now?

I have checked in the silterra130, and haven't found the PDK document.
I think you can try the way @pancho_hideboo propose. However, in general, we need PDK document when we layout and check the physical design.
 

Your DRC deck should have some off grid checks. Go ahead and draw something on a 0.0000001u grid and see what happens.
 

But I want to fabricate the chip. I dont know why my pdk does not contain design rule document.

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You have silterra 130nm?
 

I dont know why my pdk does not contain design rule document.

Because it is incomplete. You should complain to someone up the chain. You can't design without documentation... snapping is just ONE tiny issue, you will face another MILLION issues.
 

But I want to fabricate the chip. I dont know why my pdk does not contain design rule document.

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You have silterra 130nm?

I have access to silterra130nm but I have not worked in this process, only silterra180nm for now.
You can have some basic and readable information in this file, please check in advanced
Code:
your_pdk_path/silterraC13/techfile.tf

Code:
techParams(
 ;( parameter           value             )
 ;( ----------          -----             )
  ( maskGrid               0.005 )
  ( cadGrid                0.005 )
  ( drcGrid                0.005 )
  ( mfgGrid                0.005 )
  ( scale                  1.0 )
And there must be calibre or assura rule desk, you will work with that for physical verification.
But when you want to fabricate the chip, you must have the PDK document, unless it is impossible.

Because it is incomplete. You should complain to someone up the chain. You can't design without documentation... snapping is just ONE tiny issue, you will face another MILLION issues.

100% Agree.
 

thanks for your reply.

I have this techfile.tf in my silterra pdk and it contains the same code. which one shows the x snap spacing and y snap spacing?. Can you help me? is it possible for you to provide this design rules documents?
 

We use multiple snap settings.

(1) Device Layout
(2) Primitive Cell Block Layout
(3) Functional Cell Block Layout
(4) Cell Place and Route

Optimal snap is different for these.
Usually I use three different snap settings.

Set snap setting any value you like.

Post question after learning very basic things.
In your case, minimum snap is 0.005.
 

From where can I learn these basic things from. Its not even available on google. Is there any proper document on layout snap settings?
 

What you can not learn is not only snap.

I think your layout task is no more than easy PDK placement.
So snap is not so important.

BTW, how do you do Layout without Design Rule Documents ?

Before trivial snap issue, there are too many basic things you have to learn.
 
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I have recently start doing layout and came to know that the design rule documents are missing.

I have assuraDRC. tech, assuraLVS.rul file. There are more files with extension .lib etc. Are they not enought for layout design b/c when we run DRC it shows whether the layout is ok or not w.r.t. spacing etc

M I right?
 

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