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Using Verilog Tasks in VHDL Code

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mertberkea

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Hello friends,

I am currently working on designing a QSPI flash controller module. When I checked the manufacturer's page of flash, aside from flash memory model, there was a test bench environment. In this testbench environment, there is a verilog file that contains all required tasks to control the flash memory.

So here is the thing, is it possible that I can use that verilog tasks in my vhdl code? For example if I want to write to the nonvolatile configuration register of flash, I have to follow and arrange all transaction clock by clock in my vhdl code. But if I can use these verilog tasks, it will take only one line of code with a proper input argument. It will deal the transaction management by itself.

Thank you all in advance.

Regards
Mert
 

Verilog modules can be used inside VHDL. I doubt however that the testbench code is synthesizable.
 

It's highly unlikely that the task does not include any timing control statements e.g. #100, etc.

Very few tasks written for a testbench are synthesizable, the only cases where I've had synthesizable tasks is due to working around the limitations of a function having only one output. These types of combinational tasks are synthesizable but aren't useful for testbench stimulus.
 

There are problems here:
1. VHDL cannot access names inside a verilog space. While VHDL 2008 introduced external names, they are generally only supported by simulators.
2. Normal verilog does not have packages. With System Verilog, you might be able to call package tasks from VHDL, but it will depend on tool support (as it is not a standardised thing to do).
3. Others have already pointed out - these tasks are likely to be testbench only code. So no use in an FPGA.

The Verilog code you have it likely only a simulation model, not the RTL for the actual chip. The real chip would be written the same way you're having to write your VHDL to control the chip (unlikely to contain any tasks at all).
 

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