mertberkea
Newbie level 2
Hello friends,
I am currently working on designing a QSPI flash controller module. When I checked the manufacturer's page of flash, aside from flash memory model, there was a test bench environment. In this testbench environment, there is a verilog file that contains all required tasks to control the flash memory.
So here is the thing, is it possible that I can use that verilog tasks in my vhdl code? For example if I want to write to the nonvolatile configuration register of flash, I have to follow and arrange all transaction clock by clock in my vhdl code. But if I can use these verilog tasks, it will take only one line of code with a proper input argument. It will deal the transaction management by itself.
Thank you all in advance.
Regards
Mert
I am currently working on designing a QSPI flash controller module. When I checked the manufacturer's page of flash, aside from flash memory model, there was a test bench environment. In this testbench environment, there is a verilog file that contains all required tasks to control the flash memory.
So here is the thing, is it possible that I can use that verilog tasks in my vhdl code? For example if I want to write to the nonvolatile configuration register of flash, I have to follow and arrange all transaction clock by clock in my vhdl code. But if I can use these verilog tasks, it will take only one line of code with a proper input argument. It will deal the transaction management by itself.
Thank you all in advance.
Regards
Mert