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AC gain plot for a linear amplifier using CMOS inverter

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promach

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how to modify the following circuit to obtain the AC gain plot for a linear amplifier using CMOS inverter ?

Hox1O3f.png


z7fv9cN.png


I am reading some opamp loop gain testing configuration such as the following:

Q4I1Q.png
 

Don`t mix "Loop Gain" with an opamps "Open-loop gain".
 

I like the current source because then you don’t have to worry about the dc voltage on the input source. Of course you could use a giant ac coupling cap too. If you simulated at a different temp or supply, you’d need to adjust your dc level on the input slightly and refine the optimum every time. With the feedback resistor and current course you skip that step.

Someone told me the above when he suggests to use a current source stimulus instead of voltage source stimulus.

I have no idea about this. What do you guys think ?

- - - Updated - - -

Why do the phase plots show only 180 degrees ?

5eYtfQI.png
 

Why do the phase plots show only 180 degrees ?
You get out what you put in. The simulation is apparently using ideal transistor model with no internal capacitance or bandwidth limitation.
 

You are still computing gain wrong !
AC input must be coupled by a capacitor and appropriate RC time delay to self bias before AC sweep is done.

It may be >20dB but never -42dB.

Phase =180 = -180 deg = inverted is correct for an inverter.

What model is used for gm and Cm,Ciss,Coss?
WHy is V increment so coarse?

Try a better simulator.
 
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Phase =180 = -180 deg = inverted is correct for an inverter.

See the alter section on Rf1 and Rf2. This is a linear amplifier built using CMOS inverter with feedback

What model is used for gm and Cm,Ciss,Coss?

I am using BSIM 4.6.1 modelcard

And I cannot find the values of Cm, Ciss, and Coss in the modelcard. Could you suggest why ?

WHy is V increment so coarse?

You mean dc vin 0 $&vcd 0.1 ? Is 0.1 too coarse in this case ?
 

See the alter section on Rf1 and Rf2.

1) This is a linear amplifier built using CMOS inverter with feedback

2) I am using BSIM 4.6.1 modelcard

3) And I cannot find the values of Cm, Ciss, and Coss in the modelcard. Could you suggest why ?

4) You mean dc vin 0 $&vcd 0.1 ? Is 0.1 too coarse in this case ?

1) I agree, I know used these 45 yrs ago. Unbuffered 5V 20dB, buffered 60dB gain
2)3) Too many variables for me to follow, but seems valid
4) YES ! The Vss/ΔVin must be much greater than expected Av gain.


Av.jpgcmos linear.jpg Using this configuration you can breadboard testing gain vs variable Vdd with less settling time to Vin-DC , as long as you test AC gain after DC input has reached quiescent point. And not at T=0 after power on.
 
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You are still computing gain wrong !
AC input must be coupled by a capacitor and appropriate RC time delay to self bias before AC sweep is done.

It may be >20dB but never -42dB.
Capacitor coupling and self bias would be also my suggestion, but the amplifier is correctly biased in the simulation though.

Gain is -42, not -42 db.
 

1) I agree, I know used these 45 yrs ago. Unbuffered 5V 20dB, buffered 60dB gain
2)3) Too many variables for me to follow, but seems valid
4) YES ! The Vss/ΔVin must be much greater than expected Av gain.


View attachment 150855View attachment 150856 Using this configuration you can breadboard testing gain vs variable Vdd with less settling time to Vin-DC , as long as you test AC gain after DC input has reached quiescent point. And not at T=0 after power on.

I think, for ac analyses there is no "power-on" switching. This is the case for TRAN simulation only (time domain).
Before ac analyses start the program automatically finds the DC quiescent point.
 

Vss/ΔVin must be much greater than expected Av gain.

@SunnySkyguy

What is Vss in your sentence ? is it equivalent to 0 ?

And if yes, how is the dc sweep stepsize of 0.1 too course based on your sentence ?
 

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