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LPC data transfer Method

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beginner_EDA

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Hi,

I have to transfer data from A to B using 4 low pin count (LPC) I/O pins (2 from A->B and 2 from B->A).

What are the best solutions for FPGA also considering higher speed?

Regards
 
Last edited:

Vague requirements like "higher speed" are meaningless, higher than what IIC?

8B10 encoded serial LVDS if your pins allow for differential pairs and you need more than 200-300 Mbps transfers.
 

Hi,

I also vote for LVDS / SERDES.

Some FPGAs include SERDES hardware with clock recovery and so on...

Klaus
 

The LPC specification defines a clock up to 33 MHz. The LPC bus is relatively low bandwidth, well within the capabilities of modern FPGA's. Is there something special about what you're doing?
 


Hi,

you don´t say which FPGA you are talking about, thus we can´t know this.
--> you have to read the FPGA documantation whether your FPGA supports LVDS and SERDES or NOT.

Generally the document describes one way (I assume this is not the only one) to implement SERDES in a specific FPGA. So: Yes.

Klaus
 

Hi,

you don´t say which FPGA you are talking about, thus we can´t know this.

Klaus
Xilinx virtex ultrascale xcvu440-flga2892-1-c

The requirement is to use only 2 I/O pins in one directions but the link I posted above have 2 times 1 pairs of clock and 2 times 5 pairs of data lines in one direction. so much pins I don't have. Even if I reduced to only one pair of data lines, the pins for clock pair I missed.
Is it possible to pass the clock through same data lines? I just read this possibility in 8b/10b encoding mentioned by ads-ee above but I don't know how to realize that?
Any suggestion for such restriction?
 

Source synchronous data transfer with embedded clock is a popular method for fast serial interfaces (Ethernet, USB, SATA, PCIE). But it requires to extract the receiver clock from the data stream. CDR (clock and data recovery) is supported by Gigabit transceivers with respective FPGA series, for links in the lower speed range (e.g. some 100 MBPS) you need to set up your own clock extraction respectively synchronizer circuit, e.g. a software PLL. Or use oversampling clock on the receiver side.
 

For transfers in the range of 80Mbps or less you could use a data strobe (D/S) encoding. In this case clock recovery is rather trivial as it's a simple XOR of the two signals. Spacewire and IEEE1394 (i.e. Firewire) are examples of this.
 

Hi,

SN65LV1023A. This is a chip (I know you don´t need one) just to show a 10:1 SERDES connection with one pair of wires for one direction.

Check whether your FPGA is able to do something like this.


Klaus
 

Also, if you only require low bandwidth (< 1Mb/s) you could use a UART or I2C interface. The interfaces are much simpler to design and only require two pins: UART (RX/TX) and I2C (SCL/SDA).
 

Hi All,
Is this feasible then ?
Data -> 8b10b Encoder -> 10:1 serializer -> 1 pair LVDS(available 2 pins) -> 1:10 deserializer -> 8b10b Decoder -> Data
 

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