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Like it says in the text, carry chain not needed as you're only routing to a single LUT, which can be nearby
But this is a pretty old idea, as Im sure most (if not all) FPGAs now have carry chains and they pretty much all have built in multipliers, removing the need for logic mults.
I do not understand. How is carry chain not needed when only a single LUT is used here ?
I only see 4 blue register flip-flops, 1 half-adder, and 3 full-adders. Where is the LUT implemented ? You mean the AND gate itself ?
What does the 2's C (Bit serial 2's complement) block actually do ?
The carry_out flag is kept updated through the loopback on the blue register.
How does this carry_out value updating actually help in the multiplication process ?
Ok, I will use pen and pencil method to verify that the multiplier in the figure actually do multiplication correctly.
By the way, why "Routing is all nearest neighbour EXCEPT serial input which is broadcast" ? I thought the loopback update using the blue registers (ALL 4 register flip flops) requires very little routing effort by the tool ?
I do not understand. How is carry chain not needed when only a single LUT is used here ?
I only see 4 blue register flip-flops, 1 half-adder, and 3 full-adders. Where is the LUT implemented ? You mean the AND gate itself ?
Seems you forgot that LUTs are used to implement logic, therefore the LUT used is both the FA and the AND gate. All that logic fits in a single 4-input LUT...i.e. Serial_Inpuut, Xi, A, and C (4 total)
Initially, before any partial bit multiplication is started, the "2's C" block has both C_out and C_in to have values of 0, this means that the loopback update mechanism of carry does not really do anything at all for the "2's C" block (the only input ports are A and C_in , where C_in is always zero).
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