Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

PLL & CDR in Serdes 28Gbps NRZ

Status
Not open for further replies.

pankajpc

Junior Member level 1
Joined
Aug 22, 2014
Messages
19
Helped
0
Reputation
0
Reaction score
1
Trophy points
1,283
Activity points
1,436
My questions are as follows::


1. What kind of CDR to be used for 28GBPs Serdes receiver. From my own research i found out that there are 3 to 4 different options available and i am not sure which would be used.



2. Would you know of any method or technique for jitter budgeting for PLL in Tx and PLL & CDR in Rx from point of view of circuit design.The RX PLL & CDR Specs should also include the clock tree.



3. Would we prefer to use ring VCO or LC VCO for 28gbps SERDES.

4. Also does anyone have any idea of using MATLAB for Jitter Budgeting in PLL, RX, TX& CDR.

Thanks for your help in advance.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top