akbarza
Full Member level 2
hi
in attached image, i draw a circuit to clock a positive edge d-flipflop.
i have some question:
in below branch , there is three inverter. can i use only one inverter? and if i do this, is the time sufficient to reply d-flipflop as positive edge action?
for a specific clock frequency as 1Giga HZ, how do i choose the NOT and AND gate dimensions in implementation in cmos transitors? do you know a reference about this? i search google ,but i can not suitable article
thanks
in attached image, i draw a circuit to clock a positive edge d-flipflop.
i have some question:
in below branch , there is three inverter. can i use only one inverter? and if i do this, is the time sufficient to reply d-flipflop as positive edge action?
for a specific clock frequency as 1Giga HZ, how do i choose the NOT and AND gate dimensions in implementation in cmos transitors? do you know a reference about this? i search google ,but i can not suitable article
thanks