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    Clock for positive edge d-flipflop

    hi
    in attached image, i draw a circuit to clock a positive edge d-flipflop.
    i have some question:
    in below branch , there is three inverter. can i use only one inverter? and if i do this, is the time sufficient to reply d-flipflop as positive edge action?
    for a specific clock frequency as 1Giga HZ, how do i choose the NOT and AND gate dimensions in implementation in cmos transitors? do you know a reference about this? i search google ,but i can not suitable article
    thanks

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    Re: Clock for positive edge d-flipflop

    Hi,

    Most probably nobody can answer this as long as you don't provide the timing specifications for the
    * inverter
    * AND gate
    * DFF

    Klaus
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    Re: Clock for positive edge d-flipflop

    The usual reason for doing that is to make use of the propagation delay through the inverter but as Klaus stated, if we don't know what the timing should be it is difficult to confirm that hypothesis.

    Brian.
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    Re: Clock for positive edge d-flipflop

    It is possible but doesn't have too much sense, and possibly still you should add capacitance on the output of the inverter if your D-Latch hold time is higher than the delay of the inverter + and gate.
    Inverter chain is better to implement higher delay with lower consumption, to get symmetric and stable delay times at the rising and falling edges too over process and temperature variation.
    If you don't want to waste area then you should use minimal device length always, and almost minimal width. Both are technology dependent, not actually a design issue, doesn't really matter the 1GHz until it is lower than the limit of your process.
    "Try SCE to AUX." /John Aaron/



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    Re: Clock for positive edge d-flipflop

    Consider that edge sensitive flip flops are usually implemented as master slave topology circuit.



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    Re: Clock for positive edge d-flipflop

    This is a pulse generator and it works, it can clock a flop. Is it a good idea to build one? Nope.
    Really, I am not Sam.



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    Re: Clock for positive edge d-flipflop

    Hmm, interesting. I have already seen this implemented in reality and I think it wasn't too bad idea.
    It was a fix to convert bunch of D-latches to edge triggered, and we didn't have double area to create MS DFF. It was very simple solution which required small area.
    Not so elegant, but cost efficient and totally worked.
    "Try SCE to AUX." /John Aaron/



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