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  1. #1
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    Simulation in questa

    Hello, all!
    I am working on top design module on Questa. The code is like
    Code:
    module top(
    input wire ..
    output reg ..);
    reg..;
    wire..;
    When I run the simulation, It shows me the wires and registers defined between the brackets but registers and wires defined outside the module are not shown.
    And the same goes to the instantiated sub modules.
    Is there a way to show them in wave window?
    Thanks!

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  2. #2
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    Re: Simulation in questa

    You need to disable the optimizations.

    You can use the vopt command with +acc switch without any arguments to enable visibility for the entire design, or you can the +acc switch followed by what you want to be visible in the hierarchy:
    e.g. +acc+top+top.submodule

    Or you can do this on the vsim command line with vsim -voptargs=+acc+top" mydesign

    There are a number of switches to +acc that you can use to enable visibility for specific things.


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