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ESD and parasitic inductances of bond wire

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ICnow

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Hello, i have a questions about ESD protection. I was simulating HBM discharge to chip, and looking to voltage on pads. I wanted to check exceeds it breakdown voltage of gate oxide or not. As I understand exist two types of breakdown hard and soft(time-dependent gate oxide breakdown), should i worry if during esd event the voltages in chip exceeds soft breakdown? And should i worry about exceeding hard breakdown voltage, even if it really short? Or i don't need to control voltages at all only currents? And another question if i add to simulation parasitic inductances of bond wire, voltage on pads during esd event start fall with oscillations with huge amplitude(maximum voltage on pads increase from 5V - without inductances, to 40V), should i also worry about that?
 

Don't worry about the bond wires, they're a trivial fraction
of the total loop inductance.

You cannot "control" the currents, only steer them. They
are outside most technologies' voltage capability. The goal
is to return the ESD current to its source as losslessly as
possible.

I like to "set a bar" of 2X the process rated long term oxide
voltage withstand (BVox) for ESD based on experience that
microsecond-range breakdowns run more than that ratio
(to quasi-DC breakdown). But you'd be well off to qualify
that experimentally for the specific technology.
 
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    ICnow

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Thank you for reply, so the value of voltage breakdown in process specification is stated for DC voltages. For impulse signals it will be higher and better determine it experimentally. Am i right?
 

Yes, short-pulse BVox will be higher, but how much so
is something you'd like to know, not take rules-of-thumb.
Different ESD "models" impose very different pulse widths
(HBM, is more of a RC decay with a fast rise, long fall,
and for this case the middle ground wants exploring too -
particularly if using a "dynamic clamp" which might release
before the ESD source has fully discharged - this is in fact
a design feature that wants tuned to exceed the threat,
but of course also subject to "economies of layout" etc.).

I would pursue a TLP test of gate ox capacitors across
amplitude and time, get a map of first-fail, back off maybe
2X for scatter, luck and preventing "walking wounded"
for your design-to limit.
 

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