Mismatched pcie lanes ip core vs hardware.

Hello all,

I understand (ish) how pcie lanes work. I'm aware (ish) of down-plugging/ up-plugging, but I'm not entirely sure how an end point axi-pcie ip core which has been programmed to work with say for example 4x, can handle only 2x messages being sent towards it.

I'm curious how the split transactions protocol etc, can reconstruct the message.

Imagine that a connector can be plugged into two different interfaces. In one instance the FPGA shall get a 4x pcie, in the other the fpga only gets a 2x pcie.

From an FPGA point of view I wanted to just instantiate an axi_pcie core, but I'm worried about the lack of all lanes.

If I had some control over the hardware design I would have requested additional pins that could identify the connector and then load the appropriate fpga design, but for all intensive purposes I have no control or influence.

A simulation using Xilinx example design, where I've changed the generic/parameter of the root port complex such that the stimulus is 2x lane being forwarded to a 4x lane end port ip core states it's passing ID vendor, reading back configuration information (link speed, etc) AND........The transfer of data word is also passed.

Does the configuration of the ip core make any difference to the operations?

Is something happening at the lower tlp, handled entirely by Xilinx ip that I'm blind too?

Regards,
Wes

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**broken link removed**

I guess my question evolves around the physical layer/data layer and what is happening?
Why doesn't it break?

Below works
RP 1 - EP 1
RP 2 - EP 2
xxxx - EP 3
xxxx - EP 4

Below works (ish)
xxxx - EP 1
RP 1 - EP 2
RP 2 - EP 3
xxxx - EP 4

hI,

I guess my question evolves around the physical layer/data layer and what is happening?
Why doesn't it break?

Click to expand...

according to the pcie protocol , your question is about the physical layer. in physical layer specifically MAC layer.
In MAC , there is a complex fsm called link training and status state machine (LTSSM). Which will configure all the link and lanes .
(configure= assign link number,lane number, determine the common max speed of endpoint and root complex etc)
so :: according to the pcie protocol, if you connect a 4 lane device to a 2 lane device, normal data traffic will happens on two lanes and
other two lanes will be in DETECT state.(1st state of ltssm, which will find the receiver at other end).

anyway i am talking about PCIe protocol

thanks and regards