frequency divider phase

Hi Team
I have a question concerning frequency divider circuit design.
The frequency divided by 2 circuit is composed of a rising edge triggered DFF with Q_bar connected to D (as is shown in the left side of the picture)

The right side of the picture is the simulated input/output. Yellow is the reset signal. Green is the schematic simulation and red is the PEX simulation. The red input is slighted delayed then green input. However, we can see the red output, instead of slightly delayed, went through almost 180 degrees phase shift.

By analyzing the plot, I assume this is due to the PEX simulated frequency divider(red) start to work 1 period of the input signal prior to the schematic simulated output(green). This is why in the red output, the first high voltage last shorter then the later high voltages.

Can anyone let me know what decide the time that the frequency divider start to operate? In other word, how can I decide the output phase?

Thank you so much!
Allen

Both simulations are different regarding DFF propagation delay and reset input setup time.

We don't know which parameters you put in.

Hi FvM
Thanks for your reply!
I am not sure "We don't know which parameters you put in."
The DFF is realized by a mosfet circuit of 65nm techonology. The green one is only schematic and the red one is RC extracted, hence more parasitics is included. This is the reason of the different propagation delay. But the reset clock is the same.

My question is that why in green simulation, the output rises following the odd number of the input rising edge while in red simulation, the output rises following the even number of the input rising edge. (the first rising edge of red is lagged because of the reset signal)

Thanks
Allen

But the reset clock is the same.

Click to expand...

The stimulation signal timing is the same, but the required reset setup time is obviously different.

Thanks! Can you please elaborate a little?

In the attached picture, the yellow signal is the reset signal and they are the same for both simulations. According to your feedback, I think the green output signal looks correct because the output tracks the first rising edge of input after the reset clock becomes low. However, in the red simulation, the output tries to track the rising edge of the input while reset is still high...

Do you have any idea what could possibly cause that?
Thanks
Allen

However, in the red simulation, the output tries to track the rising edge of the input while reset is still high...

Click to expand...

That's a rather trivial interpretation, only based on the external waveforms shown in the simulation. You need to look at internal voltages and analyze how the reset operates. With respective internal delays, you can easily get a negative setup time of reset to clock, as it's shown in the red waveforms.