AllenD
Member level 5
Hi Team
I have a question concerning frequency divider circuit design.
The frequency divided by 2 circuit is composed of a rising edge triggered DFF with Q_bar connected to D (as is shown in the left side of the picture)
The right side of the picture is the simulated input/output. Yellow is the reset signal. Green is the schematic simulation and red is the PEX simulation. The red input is slighted delayed then green input. However, we can see the red output, instead of slightly delayed, went through almost 180 degrees phase shift.
By analyzing the plot, I assume this is due to the PEX simulated frequency divider(red) start to work 1 period of the input signal prior to the schematic simulated output(green). This is why in the red output, the first high voltage last shorter then the later high voltages.
Can anyone let me know what decide the time that the frequency divider start to operate? In other word, how can I decide the output phase?
Thank you so much!
Allen
I have a question concerning frequency divider circuit design.
The frequency divided by 2 circuit is composed of a rising edge triggered DFF with Q_bar connected to D (as is shown in the left side of the picture)
The right side of the picture is the simulated input/output. Yellow is the reset signal. Green is the schematic simulation and red is the PEX simulation. The red input is slighted delayed then green input. However, we can see the red output, instead of slightly delayed, went through almost 180 degrees phase shift.
By analyzing the plot, I assume this is due to the PEX simulated frequency divider(red) start to work 1 period of the input signal prior to the schematic simulated output(green). This is why in the red output, the first high voltage last shorter then the later high voltages.
Can anyone let me know what decide the time that the frequency divider start to operate? In other word, how can I decide the output phase?
Thank you so much!
Allen
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