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  1. #1
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    Using PLL(CD4046) to generate a 90° shifted signal, how to manage 10Hz - 1MHz?

    Hello.

    A couple of years ago or something I was getting advice here on EdaBoard about how to design a dual-channel Lock-In Amplifier(LIA) with the goal of being able to measure complex impedance across a frequency range of 10Hz - 1MHz, I was told(I have received the same answers from other places as well) that a Phase-Locked Loop(PLL) can be used to create a reference signal for the second Phase-Sensitive Detector(PSD) that is phase shifted by 90° from the original reference signal that drives the first PSD.

    But I am trying to learn about PLL's and I have chosen to look at the CD4046 first, it's datasheet states that it can manage frequencies below 1,2MHz so I know it can manage the highest frequency that I'm concerned with e.i. 1MHz. I would like to ask some questions about how to make the PLL to be able to phase shift a reference signal that will be adjusted between 10Hz and 1MHz but first I have something else to ask.

    How exactly would I use a CD4046 to phase shift a reference signal?
    I have read through these two documents which are the datasheet and an application note, but I still don't understand how this 90° phase shift function would be implemented or achieved.

    Are there anyone here who could enlighten me as to how to use a PLL to perform this task?

    Regards

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  2. #2
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    Re: Using PLL(CD4046) to generate a 90° shifted signal, how to manage 10Hz - 1MHz?

    XOR phase detector will lock when there is 90deg of phase shift between signals.



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    Re: Using PLL(CD4046) to generate a 90° shifted signal, how to manage 10Hz - 1MHz?

    Yes, but it doesn't lock over a frequency range wider than 2:1. You better run the VCO at fourfold frequency with a qudrature frequency divider, using the 4046 phase/frequency detector.



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  4. #4
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    Re: Using PLL(CD4046) to generate a 90° shifted signal, how to manage 10Hz - 1MHz?

    A first stage PLL and a /2 divider can give you the 2X
    frequency to make 0, 90, 180, 270 degree phase-field
    with a 2-bit counter behind it. But you might have to
    step away from the crusty old CD4046 to something
    with a <5um gate length. Look at "older" (like only 10
    years old) PLLs from the first couple of wireless
    generations, these will handle GHz and if you direct-drive
    the input with logic, (rather than a capacitor-blocked
    small signal RD sine wave) you have no minimum frequency.
    This does however demand a high gain and clipping, to
    get there from a small signal-under-test.



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