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  1. #1
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    Can't read value from CCP1

    #define    XTAL_FREQ    8MHZ
    #include "delay.h"
    #include "lcd.h"
    // CONFIG1H
    #pragma config OSC = HS         // Oscillator Selection bits (HS oscillator)
    #pragma config FCMEN = OFF      // Fail-Safe Clock Monitor Enable bit (Fail-Safe Clock Monitor disabled)
    #pragma config IESO = OFF       // Internal/External Oscillator Switchover bit (Oscillator Switchover mode disabled)
    // CONFIG2L
    #pragma config PWRT = ON       // Power-up Timer Enable bit (PWRT disabled)
    #pragma config BOREN = OFF      // Brown-out Reset Enable bits (Brown-out Reset disabled in hardware and software)
    #pragma config BORV = 3         // Brown Out Reset Voltage bits (Minimum setting)
    // CONFIG2H
    #pragma config WDT = OFF        // Watchdog Timer Enable bit (WDT disabled (control is placed on the SWDTEN bit))
    #pragma config WDTPS = 32768    // Watchdog Timer Postscale Select bits (1:32768)
    // CONFIG3H
    #pragma config CCP2MX = PORTC   // CCP2 MUX bit (CCP2 input/output is multiplexed with RC1)
    #pragma config PBADEN = OFF     // PORTB A/D Enable bit (PORTB<4:0> pins are configured as digital I/O on Reset)
    #pragma config LPT1OSC = OFF    // Low-Power Timer1 Oscillator Enable bit (Timer1 configured for higher power operation)
    #pragma config MCLRE = ON       // MCLR Pin Enable bit (MCLR pin enabled; RE3 input pin disabled)
    // CONFIG4L
    #pragma config STVREN = OFF      // Stack Full/Underflow Reset Enable bit (Stack full/underflow will cause Reset)
    #pragma config LVP = OFF        // Single-Supply ICSP Enable bit (Single-Supply ICSP disabled)
    #pragma config XINST = OFF      // Extended Instruction Set Enable bit (Instruction set extension and Indexed Addressing mode disabled (Legacy mode))
    // CONFIG5L
    #pragma config CP0 = OFF        // Code Protection bit (Block 0 (000800-001FFFh) not code-protected)
    #pragma config CP1 = OFF        // Code Protection bit (Block 1 (002000-003FFFh) not code-protected)
    #pragma config CP2 = OFF        // Code Protection bit (Block 2 (004000-005FFFh) not code-protected)
    #pragma config CP3 = OFF        // Code Protection bit (Block 3 (006000-007FFFh) not code-protected)
    // CONFIG5H
    #pragma config CPB = OFF        // Boot Block Code Protection bit (Boot block (000000-0007FFh) not code-protected)
    #pragma config CPD = OFF        // Data EEPROM Code Protection bit (Data EEPROM code-protected)
    // CONFIG6L
    #pragma config WRT0 = OFF       // Write Protection bit (Block 0 (000800-001FFFh) not write-protected)
    #pragma config WRT1 = OFF       // Write Protection bit (Block 1 (002000-003FFFh) not write-protected)
    #pragma config WRT2 = OFF       // Write Protection bit (Block 2 (004000-005FFFh) not write-protected)
    #pragma config WRT3 = OFF       // Write Protection bit (Block 3 (006000-007FFFh) not write-protected)
    // CONFIG6H
    #pragma config WRTC = OFF       // Configuration Register Write Protection bit (Configuration registers (300000-3000FFh) not write-protected)
    #pragma config WRTB = OFF       // Boot Block Write Protection bit (Boot block (000000-0007FFh) not write-protected)
    #pragma config WRTD = OFF       // Data EEPROM Write Protection bit (Data EEPROM not write-protected)
    // CONFIG7L
    #pragma config EBTR0 = OFF      // Table Read Protection bit (Block 0 (000800-001FFFh) not protected from table reads executed in other blocks)
    #pragma config EBTR1 = OFF      // Table Read Protection bit (Block 1 (002000-003FFFh) not protected from table reads executed in other blocks)
    #pragma config EBTR2 = OFF      // Table Read Protection bit (Block 2 (004000-005FFFh) not protected from table reads executed in other blocks)
    #pragma config EBTR3 = OFF      // Table Read Protection bit (Block 3 (006000-007FFFh) not protected from table reads executed in other blocks)
    // CONFIG7H
    #pragma config EBTRB = OFF      // Boot Block Table Read Protection bit (Boot block (000000-0007FFh) not protected from table reads executed in other blocks)
    #define sw1 PORTBbits.RB0
    unsigned long long int a122, b122, c122, d122, e122, f122, i122, j122, k122, l122, i;
    unsigned long long int rpm;
    void System_init(void) {
        TRISA = 0b00000011;
        PORTA = 0b00000011;
        ADCON1 = 0XFF;
        CMCON = 0X07;
        CCP1CON = 0X04;
        TMR1L = 0x00;
        TMR1H = 0X00;
        T1CON = 0X31;
        CCPR1L = 0X00;
        CCPR1H = 0X00;
        TRISB = 0b11111111;
        PORTB = 0b11111111;
        TRISC = 0b00000100;
        PORTC = 0b00000100;
        TRISD = 0b00000000;
        PORTD = 0b00000000;
        TRISE = 0X00;
        PORTE = 0X00;
    void rot_val_2(void) {
        a122 = rpm / 100000;
        b122 = rpm % 100000;
        c122 = b122 / 10000;
        d122 = b122 % 10000;
        e122 = d122 / 1000;
        f122 = d122 % 1000;
        i122 = f122 / 100;
        j122 = f122 % 100;
        k122 = j122 / 10;
        l122 = j122 % 10;
        lcd_goto(3, 1);
    void main(void) {
        lcd_goto(1, 1);
        lcd_puts("CCP TEST");
        while (1) {
            while (1) {
                while (!CCP1IF == 1);
                CCP1IF = 0;
                rpm = CCPR1H;
    I'm trying to design an tachometer using PIC18F4520 controller.So I tried to capture the signal from the IR SLOT sensor which fixed with the motor rotor.But I can't any output in controller.

    Negative supply from the IR sensor is connected to CCP1 pin.

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  2. #2
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    Re: Can't read value from CCP1


    * Check with a scope if the signal at the capture input pin is valid (V_IH, V_IL)
    * then check if this signal generate as catpure event

    If you need further help, you shoud show us the scope pictures and the schematic.

    Please don´t contact me via PM, because there is no time to respond to them. No friend requests. Thank you.

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  3. #3
    Advanced Member level 3
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    Jan 2015
    316 / 316

    Re: Can't read value from CCP1

    What is the clock speed? (I assume you know that the XTAL_FREQ #define only tells the 'delay' macros - which you don't use in the code you have shown - the speed you set the clock to elsewhere.)
    You have set the Timer1 up with a 1:8 prescale of the Fosc/4 source which is directly off the crystal you are using. If I assume that the XTAL_FREQ value means that you have an 8MHz crystal, then the clock into Timer 1 will be 2MHz and so the timer should increment at 250kHz or once every 4uSec. You only read the top byte of the CCPR1x registers so you effectively divide that by 65536 making the counter 3.8Hz or once every 262mSec.
    Therefore, how fast are the capture pulses supposed to be coming?
    How are you checking that you are not reading anything? Your code has no output statements - you don't call 'rot-val-2' (which seems to assume that the 'rpm' value is in decimal which is probably isn't) - so I assume you are using a debugger to read the 'rpm' variable (which you define as a 32-bit integer but only load with an 8-bit value) after setting a breakpoint at a suitable location.
    With all of the above, are you sure that you are letting the timer count for long enough between pulses?
    Also have you read Section 15.2.3 in the data sheet as you don't clear the IF bit after setting the capture mode - the first time through your main loop you could be seeing a false 'capture' that occurs faster than the timer has time to overflow into the top byte.

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