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FIFO implementation using RAM

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biju4u90

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We normally use RAM for FIFO implementation saying Flip flop implementation is costlier. How is RAM memory implemented in hardware? If RAM is implemented using normal flip flop registers, what is the use of using RAM? How RAM implementation becomes cheaper than Flip flop implementation?
 

In an ASIC, RAM would be SRAM, never from flops.
 

You would need a dual-port RAM or you would need
to accept some form of access arbitration (and make
it so). Index counters for the addresses, both. Over
and underflow flagging.

"Cheaper" means smaller area and lower power from
RAM. "How much" and "worth the effort" are worth
some considering. It will vary with the platform and
performance demands and blah blah blah. You could
go and look at FIFO memory products, chip and board
level, and get a lot of insight I expect.
 

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