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  1. #1
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    FIFO implementation using RAM

    We normally use RAM for FIFO implementation saying Flip flop implementation is costlier. How is RAM memory implemented in hardware? If RAM is implemented using normal flip flop registers, what is the use of using RAM? How RAM implementation becomes cheaper than Flip flop implementation?

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  2. #2
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    Re: FIFO implementation using RAM

    In an ASIC, RAM would be SRAM, never from flops.
    Really, I am not Sam.



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  3. #3
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    Re: FIFO implementation using RAM

    You would need a dual-port RAM or you would need
    to accept some form of access arbitration (and make
    it so). Index counters for the addresses, both. Over
    and underflow flagging.

    "Cheaper" means smaller area and lower power from
    RAM. "How much" and "worth the effort" are worth
    some considering. It will vary with the platform and
    performance demands and blah blah blah. You could
    go and look at FIFO memory products, chip and board
    level, and get a lot of insight I expect.



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  4. #4
    Junior Member level 1
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    Re: FIFO implementation using RAM

    This was discussed and explained very well about a month ago, see: https://www.edaboard.com/showthread....h-ram-or-flops



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