Output swing, threshold voltage and body effect

I have some questions regarding output voltage swing, it's relationship to the input common voltage and the threshold voltage. In the attached figure the output voltage can swing between Vout,max_swing = VDD - ISS/2 * RD (where ISS/2 is the current when the input differential voltage is zero) and Vout,min_swing= VIC - VTH.

So it follows that having a high VIC is detrimental to swing in both directions because increasing VIC increases the current and the voltage drop across RD, decreasing Vout,max_swing. A high VIC increases Vout,min_swing as well.

Now if we had diff. pair where the NMOS transistors had their own isolated pwells so that the source and bulk can be tied together. This prevents the VTH from increasing and the required bias VIC from increasing.

So is my reasoning right, here?

If we have an input diff pair in isolated wells, besides helping with PSRR or substrate noise, it also helps with output swing(?).

if we can afford the space, does tying the source and bulk of input diff pair increase the output swing?

Probably the output swing would increase, but aside from
some simple circuits like CML logic a diff pair generally runs
small signal and output swing is "Somebody Else's Problem"
(like, oh, the gain stage or the output buffer, maybe?).

Yes, twin-well or SOI do better for what you're talking
about. But whether "better" in this specific case buys you
anything valuable, for the input cost, is a question that
has to be asked in a larger context.

dick_freebird said:

Probably the output swing would increase, but aside from
some simple circuits like CML logic a diff pair generally runs
small signal and output swing is "Somebody Else's Problem"
(like, oh, the gain stage or the output buffer, maybe?).

Yes, twin-well or SOI do better for what you're talking
about. But whether "better" in this specific case buys you
anything valuable, for the input cost, is a question that
has to be asked in a larger context.

Click to expand...

Thanks for taking the time to reply. I guess if you are willing to live or can afford the extra area then isolating the input diff pair has advantages. Besides substrate noise isolation, better PSRR and higher swing, are there any other advantages you can think of ?

Hi there tenso,

May I give my take on this? Firstly, what is VIC?
I think you confused Vout_swing,max with the output common mode voltage, You can verify this because Iss is a constant value.
Since the loads are resistive, Vout max can go as high as Vdd, (M1 or M2 is off) and as low as, theoretically, 2Vds (or Vin,cm+vds,iss if Vin,cm is made to be as low as Vgs-vth)
Now the threshold of M1 or M2 does increase but I think this is Minor, but if this bothers you you can use a PMOS input since they are isolated in nwells.

**edit**
Vout can go as low as 2Vds or equivalently Vdd-IssRd