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    DAC design for 14- bit SAR ADC

    Hi All,

    I am designing Split DAC for 14-bit SAR ADC. I wanted to analyze the effect of Mismatch and process variation of the capacitor on the overall SAR ADC. For that, I wanted to run a Monte Carlo simulation on the DAC unit and I am using UMC 180nm Technology. However, I am not getting the Monte Carlo model file for MIM Cap in my PDK. If anyone can help me, it would be appreciable.
    Till I am not getting the required model file, I want to write a Monte Carlo model file for MIM cap by my own, just to get a feeling of the effect of Mismatch and process variation on the performance of overall SAR ADC. I want to write this model file and simulate it in cadence. How should I proceed? Please help.

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  2. #2
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    Re: DAC design for 14- bit SAR ADC

    Maybe you have the PDK for a related, but not proper,
    flow-variant (like, "plain digital" low cost flows might
    omit the MIM steps to save a fractional penny per die).

    You can get gross MIM scatter from PCM specs although
    these are "sandbagged", you could get them from a
    foundry modeling report / document if you asked nicely
    and signed / paid as necessary. The mismatch stuff will
    not appear in production test data almost certainly.

    You can pretty much assume that 14 bits is not going
    to happen without error correction or trimming or both,
    in this style of DAC.

    You might, in the absence of data, assert some range
    of capacitor mismatch at the size in question (itself,
    a modeling chore that may or may not have led to
    realistic L, W, area dependences of mismatch in the
    model). Say, run at 0.01%, 0.1%, 1% mismatch (use
    a gaussian multiplier to the base C value expression)
    and may as well use an analogLib capacitor as you
    are not asking about systematic variation. You could
    of course also make the generic C value include other
    variables.



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  3. #3
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    Re: DAC design for 14- bit SAR ADC

    Thanks, dick_freebird for the reply.
    I have already modeled as u said, in MATLAB. But now I wanted to do the same in Cadence. I wanted to write the monte carlo model file by adding an additional variable to the nominal value of the capacitor. This variable must follow Gaussian distribution so that each capacitor in the array can assume a different value and I can notice the effect of mismatch.
    But, I don't know how to write the model file for monte carlo simulation.
    Please help



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  4. #4
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    Re: DAC design for 14- bit SAR ADC

    Look at gauss() and agauss() and maybe track() functions.
    You can make each capacitor's C property something like
    (100p+1p*gauss(1.0, seed, blahblah)) and see statistical
    behavior.

    The sensible scaling of mismatch variation of course is the
    key to relevance, and this you'd have to extract from the
    vendor or secondhand from technical publications from same
    or similar foundry technologies.



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    Re: DAC design for 14- bit SAR ADC

    Thanks, @dick_freebird for the reply.
    I have one more query, initially, I was calculating DNL and INL as:
    1. Applying ramp input and had taken 2^N samples for N-bit.
    2. Giving the sampled input to the ADC and obtained Digital output corresponding to each input.
    3. Calculating the equivalent analog output for each digital output of ADC using ideal DAC.
    4. DNL was calculated as:
    DNL(i)= ((Vout(i+1)-Vout(i))/mean(Vout)) -1 and INL as cumulative summation of DNL.
    Is this method is correct? Because I am getting some peaks in the DNL curve of around 250LSB(image is attached).Click image for larger version. 

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    I recently came across DNL and INL calculation using the histogram. Can anybody explain me, how this works?
    Please help.



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