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VHDL compilation error "Identifier "unsigned" is not directly visible"

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engr_joni_ee

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VHDL compilation error "Identifier "unsigned" is not directly visible"

Hi,

I get an error (Identifier "unsigned" is not directly visible) while converting std_logic_vector to integer.

The signal and variable definition.

Code: 
signal s_temp : std_logic_vector (7 downto 0); 
variable i_temp : integer;

The libraries

Code: 
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

Conversion
Code: 
i_temp := to_integer(unsigned(s_temp));
 

Re: VHDL compilation error "Identifier "unsigned" is not directly visible"

std_logic_arith and numeric_std both define an unsigned type. So the compiler doesnt know which to use and hence uses neither (and you get the error).
The simple answer is to delete std_logic_arith as it is a non-standard VHDL library (std_logic_unsigned is also non-standard). std_logic_arith really should be a dead package.

the long answer is to be explicit about which one you mean:

Code: 
i_temp := to_integer(ieee.numeric_std.unsigned(s_temp));

but who wants to do all that extra typing! Just delete std_logic_arith and forget the package ever existed.
Anyone using std_logic_arith is 25 years behind the times (numeric_std was released in 1993!)
std_logic_unsigned does have uses (although non-standard) but can be replaced by using numeric_std_unsigned (released 10 years ago!)
 
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